N25Q032A13E1241F Datasheet, PDF (115/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

N25Q032 - 3 V
Instructions
Write Status Register (WRSR), Write Non Volatile Configuration Register (WRNVCR), and
Program OTP (POTP) cannot be suspended.
Except for parallelizing the instruction code on four pins (DQ0, DQ1, DQ2, DQ3) the
instruction functionality is the same as the Program/Erase Suspend (PES) instruction of the
Extended SPI protocol.
Figure 85. Program/Erase Suspend instruction sequence QIO-SPI
S
01
C
Instruction
DQ0
DQ1
DQ2
DQ3
9.3.13
Program/Erase Resume
After a Program/Erase suspend instruction, a Program/Erase Resume instruction is
required to continue performing the suspended Program or Erase sequence. Except for
parallelizing the instruction code on four pins (DQ0, DQ1, DQ2, DQ3) the instruction
functionality is the same as the Program/Erase Resume (PER) instruction of the Extended
SPI protocol.
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