N25Q032A13E1241F Datasheet, PDF (93/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

N25Q032 - 3 V
Instructions
Figure 50. Dual Command Page Program instruction sequence DIO-SPI, A2h
S
C
DQ0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
1037 1039
1036 1038
Instruction
*24-bit Address
Data Byte 1 Data Byte 2
22 20 18 16 14 12 10 8 6 4 2 0 6 4 2 0 6 4 2 0
Data Byte 256
6420
DQ1
23 21 19 17 15 13 11 9 7 5 3 1 7 5 3 1 7 5 3 1
7531
*Address bits A[23:22] are “Don’t Care.”
Figure 51. Dual Command Page Program instruction sequence DIO-SPI, D2h
S
C
DQ0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
1037 1039
1036 1038
Instruction
*24-bit Address
Data Byte 1 Data Byte 2
22 20 18 16 14 12 10 8 6 4 2 0 6 4 2 0 6 4 2 0
Data Byte 256
6420
DQ1
23 21 19 17 15 13 11 9 7 5 3 1 7 5 3 1 7 5 3 1
7531
9.2.8
*Address bits A[23:22] are “Don’t Care.”
Program OTP instruction (POTP)
The Program OTP instruction (POTP) is used to program at most 64 bytes to the OTP
memory area (by changing bits from 1 to 0, only). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been executed.
Except for parallelizing the instruction code, address, and input data on pins DQ0 and DQ1,
the instruction functionality and the locking OTP method are the same as the Program OTP
(POTP) instruction of the Extended SPI protocol.
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