N25Q032A13E1241F Datasheet, PDF (92/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Instructions
N25Q032 - 3 V
Except for the parallelizing of the instruction code on the two pins DQ0 and DQ1, the
instruction functionality is exactly the same as the Write Disable (WRDI) instruction of the
Extended SPI protocol.
Figure 48. Write Disable instruction sequence DIO-SPI
S
01234
C
Instruction
DQ0
9.2.7
S
C
DQ0
DQ1
DQ1
Dual Command Page Program (DCPP)
The Dual Command Page Program (DCPP) instruction allows to program the memory
content in DIO-SPI protocol, parallelizing the instruction code, the address and the input
data on two pins (DQ0 and DQ1). Before it can be accepted, a Write Enable (WREN)
instruction must previously have been executed. The Dual Command Page Program
(DCPP) instruction can be issued, when the device is set in DIO-SPI mode, by sending to
the memory indifferently one of the 3 instructions codes: 02h, A2h or D2h, the effect is
exactly the same. The 3 instruction codes are all accepted to help the application code
porting from Extended SPI protocol to DIO-SPI protocol.
Apart for the parallelizing on two pins of the instruction code, the Dual Command Page
Program instruction functionality is exactly the same as the Dual Input Extended Fast
Program of the Extended SPI protocol.
Figure 49. Dual Command Page Program instruction sequence DIO-SPI, 02h
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
1037 1039
1036 1038
Instruction
*24-bit Address
Data Byte 1 Data Byte 2
22 20 18 16 14 12 10 8 6 4 2 0 6 4 2 0 6 4 2 0
Data Byte 256
6420
23 21 19 17 15 13 11 9 7 5 3 1 7 5 3 1 7 5 3 1
7531
*Address bits A[23:22] are “Don’t Care.”
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