N25Q032A13E1241F Datasheet, PDF (100/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Instructions
N25Q032 - 3 V
Figure 64. Read NV Configuration Register instruction sequence DIO-SPI
S
0 1 2 3 4 5 6 7 8 9 10 11
C
Instruction
NVCR Out
Byte
Byte
DQ0
6 4 2 0 14 12 10 8
9.2.21
DQ1
7 5 3 1 15 13 11 9
LS Byte
MS Byte
Write NV Configuration Register
The Write Non Volatile Configuration register (WRNVCR) instruction allows new values to
be written to the Non Volatile Configuration register. Before it can be accepted, a write
enable (WREN) instruction must previously have been executed.
Except for the parallelizing of the instruction code and the input data on the two pins DQ0
and DQ1, the instruction functionality is exactly the same as the Write Non Volatile
Configuration Register (WNVCR) instruction of the Extended SPI protocol.
Figure 65. Write NV Configuration Register instruction sequence DIO-SPI
S
0 1 2 3 4 5 6 7 8 9 10 11
C
Instruction
NVCR In
Byte
Byte
DQ0
6 4 2 0 14 12 10 8
9.2.22
DQ1
7 5 3 1 15 13 11 9
LS Byte
MS Byte
Read Volatile Configuration Register
The Read Volatile Configuration Register (RDVCR) instruction allows the Volatile
Configuration Register to be read. See Table 5.: Volatile Configuration Register.
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