N25Q032A13E1241F Datasheet, PDF (120/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Instructions
N25Q032 - 3 V
Figure 91. Read Flag Status Register instruction sequence QIO-SPI
S
Mode 3
C _{Mode 0}
DQ0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction
Flag Status Register Out
4040 4040404040
DQ1
5151 5151515151
DQ2
6262 626 2626262
DQ3
7 3 7 3 7 37 3 7 3 7 3 7 3
9.3.19
Clear Flag Status Register
The Clear Flag Status Register (CLFSR) instruction reset the error Flag Status Register bits
(Erase Error bit, Program Error bit, VPP Error bit, Protection Error bit). It is not necessary to
set the WEL bit before the Clear Flag Status Register instruction is executed. The WEL bit
will be unchanged after this command is executed.
Figure 92. Clear Flag Status Register instruction sequence QIO-SPI
S
01
C
Instruction
DQ0
DQ1
DQ2
DQ3
9.3.20
Read NV Configuration Register
The Read Non Volatile Configuration Register (RDNVCR) instruction allows the Non Volatile
Configuration Register to be read.
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