N25Q032A13E1241F Datasheet, PDF (82/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Instructions
N25Q032 - 3 V
Figure 34. Write to Lock Register instruction sequence
S
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction
*24-Bit Address
Lock Register
In
DQ0
23 22 21
MSB
321076543210
MSB
*Address bits A23 and A22 are “Don’t Care.”
9.1.27
Table 20. Lock Register in⁽¹⁾
Sector
Bit
Value
All sectors
b7-b2
b1
b0
‘0’
Sector Lock Down bit value (refer to Table 19)
Sector Write Lock bit value (refer to Table 19)
1. Values of (b1, b0) after power-up are defined in Section 7: Protection modes.
Read Flag Status Register
The Read Flag Status Register (RFSR) instruction allows the Flag Status Register to be
read. The Status Register may be read at any time, even while a Program or Erase is in
progress. When one of these cycles is in progress, it is recommended to check the P/E
Controller bit (Not WIP) bit before sending a new instruction to the device. It is also possible
to read the Flag Register continuously, as shown here.
Figure 35. Read Flag Status Register instruction sequence
S
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
C
Instruction
DQ0
Flag Status Register Out
Flag Status Register Out
High Impedance
DQ1
76543210765432107
MSB
MSB
9.1.28
Clear Flag Status Register
The Clear Flag Status Register (CLFSR) instruction reset the error Flag Status Register bits
(Erase Error bit, Program Error bit, VPP Error bit, Protection Error bit). It is not necessary to
set the WEL bit before the Clear Flag Status Register instruction is executed. The WEL bit
will be unchanged after this command is executed.
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