N25Q032A13E1241F Datasheet, PDF(23/153 Page) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

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N25Q032A13E1241F Datasheet, PDF (23/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

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N25Q032 - 3 V

Operating features

5.1.5

5.1.6

5.1.7

5.1.8

Note:

Quad Input Fast Program

The Quad Input Fast Program (QIFP) instruction makes it possible to program up to 256

bytes using 4 input pins at the same time (by changing bits from 1 to 0).

For optimized timings, it is recommended to use the QIFP instruction to program all

consecutive targeted bytes in a single sequence rather than using several QIFP sequences

each containing only a few bytes.

Quad Input Extended Fast Program

The Quad Input Extended Fast Program (QIEFP) instruction is an enhanced version of the

Quad Input Fast Program instruction, allowing parallel input on the 4 input pins, including

the address being sent to the device.

For optimized timings, it is recommended to use the QIEFP instruction to program all

consecutive targeted bytes in a single sequence rather than using several QIEFP

sequences each containing only a few bytes.

Subsector erase, sector erase and bulk erase

The page program (PP) instruction allows bits to be reset from â1â toâ0â. In order to do this the

bytes of memory need to be erased to all 1s (FFh).

This can be achieved as follows:

z a subsector at a time, using the subsector erase (SSE) instruction. See Section 16:

Ordering information;

z a sector at a time, using the sector erase (SE) instruction;

z throughout the entire memory, using the bulk erase (BE) instruction.

This starts an internal erase cycle (of duration tSSE, tSE or tBE). The erase instruction must

be preceded by a write enable (WREN) instruction.

Polling during a write, program or erase cycle

A further improvement in the time to Write Status Register (WRSR), POTP, PP,

DIFP,DIEFP,QIFP, QIEFP or Erase (SSE, SE or BE) can be achieved by not waiting for the

worst case delay (tW, tPP, tSSE, tSE, or tBE). The application program can monitor if the

required internal operation is completed, by polling the dedicated register bits to establish

when the previous Write, Program or Erase cycle is complete.

The information on the memory being in progress for a Program, Erase, or Write instruction

can be checked either on the Write In Progress (WIP) bit of the Status Register or in the

Program/Erase Controller bit of the Flag Status Register.

The Program/Erase Controller bit is the opposite state of the WIP bit in the Status Register.

In the Flag Status Register additional information can be checked, as eventual

Program/Erase failures by mean of the Program or erase Error bits.

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

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