N25Q032A13E1241F Datasheet, PDF (64/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Instructions
N25Q032 - 3 V
9.1.10
Write Enable (WREN)
The Write Enable (WREN) instruction sets the Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set prior to every Program or Erase instruction:
Page Program (PP), Dual Input Fast Program (DIFP), Dual Input Extended Fast Program
(DIEFP), Quad Input Fast Program (QIFP), Quad Input Extended Fast Program (QIEFP),
Program OTP (POTP), Write to Lock Register (WRLR), Subsector Erase (SSE), Sector
Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Write Volatile Configuration
Register (WRVCR), Write Volatile Enhanced Configuration Register (WRVECR) and Write
NV Configuration Register (WRNVCR) instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
At the end of the POR sequence the WEL bit is low, so the next modify instruction can be
accepted.
Figure 19. Write Enable instruction sequence
S
C
DQ0
01234567
Instruction
9.1.11
DQ1
High Impedance
Write Disable (WRDI)
AI13731
The Write Disable (WRDI) instruction resets the Write Enable Latch (WEL) bit. The Write
Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the instruction
code, and then driving Chip Select (S) High.
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