N25Q032A13E1241F Datasheet, PDF (128/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

XIP Operations
N25Q032 - 3 V
10.1
Enter XIP mode by setting the Non Volatile Configuration
Register
To use the Non Volatile Configuration Register method to enter in XIP mode it is necessary
to set the Non Volatile Configuration Register bits from 11 to 9 with the pattern
corresponding to the required XIP mode by mean of the Write Non Volatile Configuration
Register (WRNVCR) instruction. (See Table 23.: NVCR XIP bits setting example.)
This instruction doesn't affect the XIP state until the next Power on sequence. In this case,
after the next power on sequence, the memory directly accept addresses and then, after the
dummy clock cycles (configurable), outputs the data as described in Table 23.: NVCR XIP
bits setting example. For example to enable XIP on QIOFR in normal SPI protocol with six
dummy clock cycles the following pattern must be issued:
Table 23. NVCR XIP bits setting example
B1h
(WRNVCR
+ 0110
100
111
opcode)
6 dummy cycles
for fast read
instructions
XIP set as
default; Quad
I/O mode
Output Buffer
driver strength
default
x
1
11
Don’t Care
Hold/Reset
not disabled
Extended
SPI protocol
xx
Don’t
Care
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