N25Q032A13E1241F Datasheet, PDF (95/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

N25Q032 - 3 V
Instructions
Figure 54. Sector Erase instruction sequence DIO-SPI
S
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
C
DQ0
Instruction
*24-bit Address
22 20 18 16 14 12 10 8 6 4 2 0
DQ1
23 21 19 17 15 13 11 9 7 5 3 1
9.2.11
Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to '1' (FFh). Before it can be accepted, a Write
Enable (WREN) instruction must previously have been executed.
Except for the parallelizing of the instruction code on the two pins DQ0 and DQ1, the
instruction functionality is exactly the same as the Bulk Erase (BE) instruction of the
Extended SPI protocol.
Figure 55. Bulk Erase instruction sequence DIO-SPI
S
0123
C
Instruction
DQ0
DQ1
9.2.12
Program/Erase Suspend
The Program/Erase Suspend (PES) instruction allows the controller to interrupt a Program
or an Erase instruction, in particular: Subsector Erase (SSE), Sector Erase (SE) and Dual
Command Page Program (DCPP) can be suspended and resumed while Bulk Erase (BE),
Write Status Register (WRSR), Write Non Volatile Configuration Register (WRNVCR), and
Program OTP (POTP) cannot be suspended.
Apart for the parallelizing of the instruction code on the two pins DQ0 and DQ1, the
instruction functionality is exactly the same as the Program/Erase Suspend (PES)
instruction of the Extended SPI protocol.
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