N25Q032A13E1241F Datasheet, PDF(20/153 Page) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

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N25Q032A13E1241F Datasheet, PDF (20/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

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SPI Protocols

N25Q032 - 3 V

The N25Q032 memory can work with 3 different Serial protocols:

z Extended SPI protocol.

z Dual I/O SPI (DIO-SPI) protocol.

z Quad I/O SPI (QIO-SPI) protocol.

It is possible to choose among the three protocols by means of user volatile or non-volatile

configuration bits.It's not possible to mix Extended SPI, DIO-SPI, and QIO-SPI protocols.

The device can operate in XIP mode in all 3 protocols.

4.1

Extended SPI protocol

This is an extension of the standard (legacy) SPI protocol. Instructions are transmitted on a

single data line (DQ0), while addresses and data are transmitted by one, two or four data

lines (DQ0, DQ1, W/VPP(DQ2) and HOLD / (DQ3) according to the instruction.

When used in the Extended SPI protocol, these devices can be driven by a micro controller

in either of the two following modes:

z CPOL=0, CPHA=0

z CPOL=1, CPHA=1

Please refer to the SPI modes for a detailed description of these two modes

4.2

Note:

Dual I/O SPI (DIO-SPI) protocol

Dual I/O SPI (DIO-SPI) protocol: instructions, addresses and I/O data are always

transmitted on two data lines (DQ0 and DQ1).

Also when in DIO-SPI mode, the device can be driven by a micro controller in either of the

two following modes:

z CPOL= 0, CPHA= 0

z CPOL= 1, CPHA= 1

Please refer to the SPI modes for a detailed description of these two modes.

Extended SPI protocol Dual I/O instructions allow only address and data to be transmitted

over two data lines. However, DIO-SPI allows instructions, addresses, and data to be

transmitted on two data lines.

This mode can be set using two ways

z Volatile: by setting bit 6 of the VECR to 0. The device enters DIO-SPI protocol

immediately after the Write Enhanced Volatile Configuration Register sequence

completes. The device returns to the default working mode (defined by NVCR) on

power on.

z Default/ Non-Volatile: This is default mode on power-up. By setting bit 2 of the NVCR

to 0. The device enters DIO-SPI protocol on the subsequent power-on. After all

subsequent power-on sequences, the device still starts in DIO-SPI protocol unless bit 2

of NVCR is set to 1 (default value, corresponding to Extended SPI protocol) or bit 3 of

NVCR is set to 0 (corresponding to QIO-SPI protocol).

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

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