PIC18F2331 Datasheet, PDF (91/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
8.0 8 X 8 HARDWARE MULTIPLIER
8.1 Introduction
An 8 x 8 hardware multiplier is included in the ALU of
the PIC18F2331/2431/4331/4431 devices. By making
the multiply a hardware operation, it completes in a
single instruction cycle. This is an unsigned multiply
that gives a 16-bit result. The result is stored into the
16-bit product register pair (PRODH:PRODL). The
multiplier does not affect any flags in the Status
register.
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
• Higher computational throughput
• Reduces code size requirements for multiply
algorithms
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
Table 8-1 shows a performance comparison between
enhanced devices using the single cycle hardware mul-
tiply, and performing the same function without the
hardware multiply.
TABLE 8-1: PERFORMANCE COMPARISON
Routine
Multiply Method
Program
Memory
(Words)
Without hardware multiply
13
8 x 8 unsigned
Hardware multiply
1
Without hardware multiply
33
8 x 8 signed
Hardware multiply
6
Without hardware multiply
21
16 x 16 unsigned
Hardware multiply
24
Without hardware multiply
52
16 x 16 signed
Hardware multiply
36
Cycles
(Max)
69
1
91
6
242
24
254
36
Time
@ 40 MHz
6.9 µs
100 ns
9.1 µs
600 ns
24.2 µs
2.4 µs
25.4 µs
3.6 µs
@ 10 MHz
27.6 µs
400 ns
36.4 µs
2.4 µs
96.8 µs
9.6 µs
102.6 µs
14.4 µs
@ 4 MHz
69 µs
1 µs
91 µs
6 µs
242 µs
24 µs
254 µs
36 µs
8.2 Operation
Example 8-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
Example 8-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s Most Significant bit (MSb) is tested
and the appropriate subtractions are done.
EXAMPLE 8-1:
8 x 8 UNSIGNED
MULTIPLY ROUTINE
MOVF
MULWF
ARG1, W
ARG2
;
; ARG1 * ARG2 ->
; PRODH:PRODL
EXAMPLE 8-2:
8 x 8 SIGNED MULTIPLY
ROUTINE
MOVF
MULWF
BTFSC
SUBWF
MOVF
BTFSC
SUBWF
ARG1, W
ARG2
ARG2, SB
PRODH, F
ARG2, W
ARG1, SB
PRODH, F
; ARG1 * ARG2 ->
; PRODH:PRODL
; Test Sign Bit
; PRODH = PRODH
;
- ARG1
; Test Sign Bit
; PRODH = PRODH
;
- ARG2
 2003 Microchip Technology Inc.
Preliminary
DS39616B-page 89