PIC18F2331 Datasheet, PDF (209/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
17.12.3 PWM OUTPUTS WHILE IN FAULT
CONDITION
While in the fault state (i.e., one or both FLTA and FLTB
inputs are active), the PWM output signals are driven
into their inactive states. The selection of which PWM
outputs are deactivated (while in the fault state) is
determined by the FLTCON bit in the FLTCONFIG
register as follows:
• FLTCON = 1. When FLTA or FLTB is asserted,
the PWM outputs (i.e., PWM[7:0]) are driven into
their inactive state
• FLTCON = 0. When FLTA or FLTB is asserted,
only PWM[5:0] outputs are driven inactive, leaving
PWM[7:6] activated.
Note:
Disabling only three PWM channels and
leaving one PWM channel enabled when
in the fault state, allows the flexibility to
have at least one PWM channel enabled.
None of the PWM outputs can be enabled
(driven with the PWM Duty Cycle regis-
ters) while FLTCON = 1 and the fault con-
dition is present.
17.12.4 PWM OUTPUTS IN DEBUG MODE
The BRFEN bit in the FLTCONFIG register controls the
simulation of fault condition when a breakpoint is hit,
while debugging the application using a In-Circuit
Emulator (ICE) or a In-Circuit Debugger (ICD). Setting
the BRFEN to high, enables the fault condition on
breakpoint, thus driving the PWM outputs to inactive
state. This is done to avoid any continuous keeping of
status on the PWM pin, which may result in damage of
the power devices connected to the PWM outputs.
If BRFEN = 0, the fault condition on breakpoint is
disabled.
Note:
It is highly recommended to enable the
fault condition on breakpoint if a debug-
ging tool is used, while developing the
firmware and the high-power circuitry is
used. When the device is ready to pro-
gram after debugging the firmware,
BRFEN bit can be disabled.
 2003 Microchip Technology Inc.
Preliminary
DS39616B-page 207