PIC18F2331 Datasheet, PDF (67/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
5.9.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and Peripheral Modules for control-
ling the desired operation of the device. These regis-
ters are implemented as static RAM. A list of these
registers is given in Table 5-1 and Table 5-2.
The SFRs can be classified into two sets; those asso-
ciated with the “core” function and those related to the
peripheral functions. Those registers related to the
“core” are described in this section, while those related
to the operation of the peripheral features are
described in the section of that peripheral feature.
The SFRs are typically distributed among the
peripherals whose functions they control.
The unused SFR locations will be unimplemented and
read as ‘0’s.
TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2331/2431/4331/4431 DEVICES
Address Name Address Name Address
FFFh TOSU
FDFh INDF2
FBFh
FFEh TOSH
FDEh POSTINC2
FBEh
FFDh TOSL
FDDh POSTDEC2 FBDh
FFCh STKPTR
FDCh PREINC2
FBCh
FFBh PCLATU
FFAh PCLATH
FDBh PLUSW2
FDAh FSR2H
FBBh
FBAh
FF9h PCL
FD9h FSR2L
FB9h
FF8h TBLPTRU
FD8h STATUS
FB8h
FF7h TBLPTRH
FD7h TMR0H
FB7h
FF6h TBLPTRL
FD6h TMR0L
FB6h
FF5h TABLAT
FF4h PRODH
FD5h
FD4h
T0CON
—
FB5h
FB4h
FF3h PRODL
FD3h OSCCON
FB3h
FF2h INTCON
FD2h LVDCON
FB2h
FF1h INTCON2
FD1h WDTCON
FB1h
FF0h INTCON3
FD0h RCON
FB0h
FEFh INDF0
FCFh TMR1H
FAFh
FEEh POSTINC0
FCEh TMR1L
FAEh
FEDh POSTDEC0 FCDh T1CON
FADh
FECh PREINC0
FEBh PLUSW0
FCCh
FCBh
TMR2
PR2
FACh
FABh
FEAh FSR0H
FCAh T2CON
FAAh
FE9h FSR0L
FC9h SSPBUF
FA9h
FE8h WREG
FC8h SSPADD
FA8h
FE7h INDF1
FE6h POSTINC1
FC7h SSPSTAT
FC6h SSPCON
FA7h
FA6h
FE5h POSTDEC1
FC5h
—
FA5h
FE4h PREINC1
FC4h ADRESH
FA4h
FE3h PLUSW1
FC3h ADRESL
FA3h
FE2h
FE1h
FSR1H
FSR1L
FC2h ADCON0
FC1h ADCON1
FA2h
FA1h
FE0h BSR
FC0h ADCON2
FA0h
Name
CCPR1H
CCPR1L
CCP1CON
CCPR2H
CCPR2L
CCP2CON
ANSEL1
ANSEL0
T5CON
QEICON
—
—
—
—
—
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
RCSTA
BAUDCTL
EEADR
EEDATA
EECON2
EECON1
IPR3
PIR3
PIE3
IPR2
PIR2
PIE2
Address
F9Fh
F9Eh
F9Dh
F9Ch
F9Bh
F9Ah
F99h
F98h
F97h
F96h
F95h
F94h
F93h
F92h
F91h
F90h
F8Fh
F8Eh
F8Dh
F8Ch
F8Bh
F8Ah
F89h
F88h
F87h
F86h
F85h
F84h
F83h
F82h
F81h
F80h
Name
IPR1
PIR1
PIE1
—
OSCTUNE
ADCON3
ADCHS
—
—
TRISE
TRISD
TRISC
TRISB
TRISA
PR5H
PR5L
—
—
LATE
LATD
LATC
LATB
LATA
TMR5H
TMR5L
—
—
PORTE
PORTD
PORTC
PORTB
PORTA
Address Name
F7Fh
PTCON0
F7Eh
PTCON1
F7Dh
PTMRL
F7Ch
PTMRH
F7Bh
F7Ah
PTPERL
PTPERH
F79h
PDC0L
F78h
PDC0H
F77h
PDC1L
F76h
PDC1H
F75h
PDC2L
F74h
PDC2H
F73h
PDC3L
F72h
PDC3H
F71h SEVTCMPL
F70h SEVTCMPH
F6Fh PWMCON0
F6Eh PWMCON1
F6Dh
DTCON
F6Ch
F6Bh
FLTCONFIG
OVDCOND
F6Ah OVDCONS
F69h CAP1BUFH
F68h CAP1BUFL
F67h
F66h
CAP2BUFH
CAP2BUFL
F65h CAP3BUFH
F64h CAP3BUFL
F63h CAP1CON
F62h
F61h
CAP2CON
CAP3CON
F60h DFLTCON
 2003 Microchip Technology Inc.
Preliminary
DS39616B-page 65