PIC18F2331 Datasheet, PDF (198/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
17.6.2 DUTY CYCLE REGISTER BUFFERS
The four PWM Duty Cycle registers are
double-buffered to allow glitchless updates of the PWM
outputs. For each duty cycle block, there is a Duty
Cycle Buffer register that is accessible by the user and
a second Duty Cycle register that holds the actual
compare value used in the present PWM period.
In edge-aligned PWM Output mode, a new duty cycle
value will be updated whenever a PTMR match with the
PTPER register occurs and PTMR is reset as shown in
Figure 17-12. Also, the contents of the duty cycle
buffers are automatically loaded into the Duty Cycle
registers when the PWM time base is disabled
(PTEN = 0).
When the PWM time base is in the Up/Down Counting
mode, new duty cycle values will be updated when the
value of the PTMR register is zero and the PWM time
base begins to count upwards. The contents of the duty
cycle buffers are automatically loaded into the Duty
Cycle registers when the PWM time base is disabled
(PTEN = 0). Figure 17-13 shows the timings when the
duty cycle update occur for the Up/Down Count mode.
In this mode, up to one entire PWM period is available
for calculating and loading the new PWM duty cycle
before changes take effect.
When the PWM time base is in the Up/Down Counting
mode with double updates, new duty cycle values will
be updated when the value of the PTMR register is zero
and when the value of the PTMR register matches the
value in the PTPER register. The contents of the duty
cycle buffers are automatically loaded into the Duty
Cycle registers during both of the above said
conditions. Figure 17-14 shows the duty cycle updates
for Up/Down mode with double update. In this mode,
only up to half of a PWM period is available for
calculating and loading the new PWM duty cycle before
changes take effect.
17.6.3 EDGE-ALIGNED PWM
Edge-aligned PWM signals are produced by the
module when the PWM time base is in the Free
Running mode or the Single-shot mode. For
edge-aligned PWM outputs, the output for a given
PWM channel has a period specified by the value
loaded in PTPER and a duty cycle specified by the
appropriate Duty Cycle register (see Figure 17-12).
The PWM output is driven active at the beginning of the
period (PTMR = 0) and is driven inactive when the
value in the Duty Cycle register matches PTMR. A new
cycle is started when PTMR matches the PTPER as
explained in the PWM period section.
If the value in a particular Duty Cycle register is zero,
then the output on the corresponding PWM pin will be
inactive for the entire PWM period. In addition, the out-
put on the PWM pin will be active for the entire PWM
period if the value in the Duty Cycle register is greater
than the value held in the PTPER register.
FIGURE 17-12:
EDGE-ALIGNED PWM
New Duty Cycle Latched
PTPER
PDC PTMR
(old) Value
PDC
(new)
0
Duty Cycle
Active at
beginning
of period
Period
FIGURE 17-13:
DUTY CYCLE UPDATE TIMES IN UP/DOWN COUNTING MODE
Duty cycle value loaded from buffer register
PWM output
PTMR Value
New value written to duty cycle buffer
DS39616B-page 196
Preliminary
 2003 Microchip Technology Inc.