PIC18F2331 Datasheet, PDF (391/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
Example SPI Master Mode (CKE = 0) ..................... 361
Example SPI Master Mode (CKE = 1) ..................... 362
Example SPI Slave Mode (CKE = 0) ....................... 363
Example SPI Slave Mode (CKE = 1) ....................... 364
External Clock (All Modes except PLL) .................... 355
Fail-Safe Clock Monitor ............................................ 282
I²C Bus Data ............................................................ 365
I²C Bus Start/Stop Bits ............................................. 365
I²C Reception (7-bit Address) .................................. 219
I²C Transmission (7-bit Address) ............................. 219
Low-Voltage Detect .................................................. 264
Low-Voltage Detect Characteristics ......................... 352
Master SSP I²C Bus Data ........................................ 367
Master SSP I²C Bus Start/Stop Bits ........................ 367
PWM Output ............................................................ 156
Reset, Watchdog Timer (WDT), Oscillator Start-up
Timer (OST), Power-up Timer (PWRT) ........... 358
Send Break Character Sequence ............................ 236
Slow Rise Time (MCLR Tied to VDD,
VDD Rise > TPWRT) ............................................ 55
SPI Mode (Master Mode) ......................................... 215
SPI Mode (Slave Mode with CKE = 0) ..................... 215
SPI Mode (Slave Mode with CKE = 1) ..................... 216
Synchronous Reception (Master Mode, SREN) ...... 239
Synchronous Transmission ...................................... 237
Synchronous Transmission (Through TXEN) .......... 238
Time-out Sequence on POR w/PLL Enabled
(MCLR Tied to VDD) ........................................... 55
Time-out Sequence on Power-up (MCLR Not
Tied to VDD): Case 1 .......................................... 54
Time-out Sequence on Power-up (MCLR Not
Tied to VDD): Case 2 .......................................... 54
Time-out Sequence on Power-up (MCLR
Tied to VDD, VDD Rise < TPWRT) ........................ 54
Timer0 and Timer1 External Clock .......................... 359
Transition for Entry to SEC_IDLE Mode .................... 36
Transition for Entry to SEC_RUN Mode .................... 38
Transition for Entry to Sleep Mode ............................ 34
Transition for Two-Speed Start-up
(INTOSC to HSPLL) ......................................... 280
Transition for Wake from RC_RUN Mode
(RC_RUN to NFP) ............................................. 37
Transition for Wake from SEC_RUN Mode
(Secondary Clock to HSPLL) ............................. 36
Transition for Wake from Sleep (HSPLL) ................... 34
Transition Timing For Wake From PRI_IDLE Mode ... 35
Transition Timing to PRI_IDLE Mode ........................ 35
Transition to RC_IDLE Mode ..................................... 37
Transition to RC_RUN Mode ..................................... 39
USART Synchronous Receive ( Master/Slave) ........ 369
USART SynchronousTransmission
(Master/Slave) .................................................. 369
Timing Diagrams and Specifications ................................ 355
Capture/Compare/PWM Requirements ................... 360
CLKO and I/O Requirements ................................... 357
DC Characteristics - Internal RC Accuracy .............. 356
Example SPI Mode Requirements
(Master Mode, CKE = 0) .................................. 361
Example SPI Mode Requirements
(Master Mode, CKE = 1) .................................. 362
Example SPI Mode Requirements
(Slave Mode, CKE = 0) .................................... 363
Example SPI Slave Mode Requirements
(CKE = 1) ......................................................... 364
External Clock Requirements .................................. 355
I²C Bus Data Requirements (Slave Mode) .............. 366
Master SSP I²C Bus Data Requirements ................ 368
Master SSP I²C Bus Start/Stop Bits
Requirements .................................................. 367
PLL Clock ................................................................ 356
RESET, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................ 358
Timer0 and Timer1 External Clock Requirements ... 359
USART Synchronous Receive Requirements ......... 369
USART Synchronous Transmission
Requirements .................................................. 369
Top-of-Stack Access .......................................................... 58
TSTFSZ ........................................................................... 328
Two-Speed Start-up ..................................................267, 279
Two-Word Instructions
Example Cases .......................................................... 62
TXSTA Register
BRGH Bit ................................................................. 225
U
UA .................................................................................... 212
Update Address bit, UA ................................................... 212
USART
Asynchronous Mode ................................................ 230
12-bit Break Transmit and Receive ................. 236
Associated Registers, Receive ........................ 234
Associated Registers, Transmit ....................... 232
Auto-Wake-up on Sync Break ......................... 235
Receiver .......................................................... 233
Setting up 9-bit Mode with Address Detect ..... 233
Transmitter ...................................................... 230
Baud Rate Generator (BRG) ................................... 225
Associated Registers ....................................... 226
Auto-Baud Rate Detect .................................... 229
Baud Rate Error, Calculating ........................... 225
Baud Rates, Asynchronous Modes ................. 226
High Baud Rate Select (BRGH Bit) ................. 225
Power-Managed Mode Operation ................... 225
Sampling .......................................................... 225
Serial Port Enable (SPEN Bit) ................................. 221
Synchronous Master Mode ...................................... 237
Associated Registers, Reception ..................... 240
Associated Registers, Transmit ....................... 238
Reception ........................................................ 239
Transmission ................................................... 237
Synchronous Slave Mode ........................................ 241
Associated Registers, Receive ........................ 242
Associated Registers, Transmit ....................... 241
Reception ........................................................ 242
Transmission ................................................... 241
W
Watchdog Timer (WDT) ............................................267, 278
Associated Registers ............................................... 279
Control Register ....................................................... 278
During Oscillator Failure .......................................... 281
Programming Considerations .................................. 278
WCOL bit ......................................................................... 213
Write Collision Detect bit (WCOL) ................................... 213
WWW, On-Line Support ...................................................... 6
X
XORLW ............................................................................ 328
XORWF ........................................................................... 329
 2003 Microchip Technology Inc.
DS39616B-page 389