PIC18F2331 Datasheet, PDF (178/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
16.2.6.1 Velocity Event Timing
The event pulses are reduced by a fixed ratio by the
velocity pulse divider. The divider is useful for
high-speed measurements where the velocity events
happen frequently. By producing a single output pulse
for a given number of input event pulses, the counter
can track larger pulse counts (i.e., distance travelled)
for a given time interval. Time is measured by utilizing
the TMR5 time base.
Each velocity pulse serves as a capture pulse. With the
TMR5 in Synchronous Timer mode, the value of TMR5
is captured on every output pulse of the postscaler. The
counter is subsequently reset to ‘0’. TMR5 is reset
upon a capture event.
Figure 16-13 shows the velocity measurement timing
diagram.
FIGURE 16-12: VELOCITY MEASUREMENT BLOCK DIAGRAM
QEI
Control
Logic
Reset ^{TMR5 Reset}
Logic
TMR5 ^Clock
16
TCY
Velocity Mode
CAP3/QEB
CAP2/QEA
CAP1/INDX
Velocity Event
QEB
QEA
INDX
Direction
Clock
Velocity Capture
Postscaler
IC1
(VELR Register)
Position
Counter
DS39616B-page 176
Preliminary
 2003 Microchip Technology Inc.