PIC18F2331 Datasheet, PDF (281/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
TABLE 22-2: SUMMARY OF WATCHDOG TIMER REGISTERS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
CONFIG2H
—
—
WINEN WDTPS3
RCON
IPEN
—
—
RI
WDTCON
WDTW
—
—
—
Legend: Shaded cells are not used by the Watchdog Timer.
WDTPS2
TO
—
Bit 2
WDTPS2
PD
—
Bit 1
WDTPS0
POR
—
Bit 0
WDTEN
BOR
SWDTEN
22.3 Two-Speed Start-up
The Two-Speed Start-up feature helps to minimize the
latency period from oscillator start-up to code execution
by allowing the microcontroller to use the INTRC oscil-
lator as a clock source until the primary clock source is
available. It is enabled by setting the IESO bit in
Configuration Register 1H (CONFIG1H<7>).
Two-Speed Start-up is available only if the primary
Oscillator mode is LP, XT, HS or HSPLL (crystal-based
modes). Other sources do not require a OST start-up
delay; for these, Two-Speed Start-up is disabled.
When enabled, Resets and wake-ups from Sleep mode
cause the device to configure itself to run from the inter-
nal oscillator block as the clock source, following the
time-out of the Power-up Timer after a POR Reset is
enabled. This allows almost immediate code execu-
tion, while the primary oscillator starts and the OST is
running. Once the OST times out, the device automat-
ically switches to PRI_RUN mode.
Because the OSCCON register is cleared on Reset
events, the INTOSC (or postscaler) clock source is not
initially available after a Reset event; the INTRC clock
is used directly at its base frequency. To use a higher
clock speed on wake-up, the INTOSC or postscaler
clock sources can be selected to provide a higher clock
speed by setting bits IFRC2:IFRC0 immediately after
Reset. For wake-ups from Sleep, the INTOSC or
postscaler clock sources can be selected by setting
IFRC2:IFRC0 prior to entering Sleep mode.
In all other power-managed modes, Two-Speed Start-
up is not used. The device will be clocked by the cur-
rently selected clock source until the primary clock
source becomes available. The setting of the IESO bit
is ignored.
22.3.1 SPECIAL CONSIDERATIONS FOR
USING TWO-SPEED START-UP
While using the INTRC oscillator in Two-Speed Start-
up, the device still obeys the normal command
sequences for entering power-managed modes,
including serial SLEEP instructions (refer to
Section 3.1.3 “Multiple Sleep Commands”). In prac-
tice, this means that user code can change the
SCS1:SCS0 bit settings and issue SLEEP commands
before the OST times out. This would allow an applica-
tion to briefly wake-up, perform routine “housekeeping”
tasks and return to Sleep before the device starts to
operate from the primary oscillator.
User code can also check if the primary clock source is
currently providing the system clocking by checking the
status of the OSTS bit (OSCCON<3>). If the bit is set,
the primary oscillator is providing the system clock.
Otherwise, the internal oscillator block is providing the
clock during wake-up from Reset or Sleep mode.
 2003 Microchip Technology Inc.
Preliminary
DS39616B-page 279