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PIC18F2331 Datasheet, PDF (307/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D | |||
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PIC18F2331/2431/4331/4431
CPFSGT
Compare f with W, skip if f > W
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
[ label ] CPFSGT f [,a]
0 ⤠f ⤠255
a â [0,1]
(f) â (W),
skip if (f) > (W)
(unsigned comparison)
None
0110 010a ffff ffff
Compares the contents of data
memory location âfâ to the contents
of the W by performing an
unsigned subtraction.
If the contents of âfâ are greater than
the contents of WREG, then the
fetched instruction is discarded and
a NOP is executed instead, making
this a two-cycle instruction. If âaâ is
0, the Access Bank will be
selected, overriding the BSR value.
If âaâ = 1, then the bank will be
selected as per the BSR value
(default).
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register âfâ
Process
Data
If skip:
Q1
Q2
Q3
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q4
No
operation
Q4
No
operation
No
operation
Example:
HERE
CPFSGT REG
NGREATER :
GREATER :
Before Instruction
PC
=
W
=
Address (HERE)
?
After Instruction
If REG
PC
If REG
PC
> W;
= Address (GREATER)
⤠W;
= Address (NGREATER)
CPFSLT
Compare f with W, skip if f < W
Syntax:
[ label ] CPFSLT f [,a]
Operands:
0 ⤠f ⤠255
a â [0,1]
Operation:
(f) â (W),
skip if (f) < (W)
(unsigned comparison)
Status Affected: None
Encoding:
0110 000a ffff ffff
Description:
Compares the contents of data
memory location âfâ to the contents
of W by performing an unsigned
subtraction.
If the contents of âfâ are less than
the contents of W, then the fetched
instruction is discarded and a NOP
is executed instead, making this a
two-cycle instruction. If âaâ is 0, the
Access Bank will be selected. If âaâ
is 1, the BSR will not be overridden
(default).
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Decode
Read
register âfâ
If skip:
Q1
Q2
Q3
Process
Data
Q3
Q4
No
operation
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
NLESS
LESS
CPFSLT REG
:
:
Before Instruction
PC
=
W
=
Address (HERE)
?
After Instruction
If REG
PC
If REG
PC
< W;
= Address (LESS)
⥠W;
= Address (NLESS)
 2003 Microchip Technology Inc.
Preliminary
DS39616B-page 305
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