PIC18F2331 Datasheet, PDF (179/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
FIGURE 16-13:
VELOCITY MEASUREMENT TIMING⁽¹⁾
Forward
QEA
QEB
vel_out
velcap
TMR5⁽²⁾
Reverse
VELR⁽²⁾
cnt_reset⁽³⁾
Old Value
1529
1537
IC1IF⁽⁴⁾
Q1
Q1
Q1
CAP1REN
Instr.
Execution
BCF TMR5CON, VELM
BCF PIE2, IC1IE
BSF PIE2, IC1IE
MOVWF QEICON⁽⁵⁾
Note 1: Timing shown is for QEIM<2:0> = 101, 110 or 111 (x4 Update mode enabled) and the velocity postscaler divide ratio
is set to divide by 4 (PDEC<1:0> = 01).
2: VELR register latches the TMR5 count on the “velcap” capture pulse. Timer5 must be set to the synchronous timer or
Counter mode. In this example, it is set to the Synchronous Timer mode where the TMR5 prescaler divide ratio = 1
(i.e., Timer5 clock = TCY).
3: The TMR5 counter is reset on the next Q1 clock cycle following the “velcap” pulse. TMR5 value is unaffected when the
Velocity Measurement mode is first enabled (VELM = 0). The velocity postscaler values must be reconfigured to their
previous settings when re-entering Velocity Measurement mode. While making speed measurements of very slow
rotational speeds (e.g., servo-controller applications), the Velocity Measurement mode may not provide sufficient
precision. The Pulse Width Measurement mode may have to be used to provide the additional precision. In this case,
the input pulse is measured on the CAP1 input pin.
4: IC1IF interrupt is enabled by setting IC1IE as follows, BSF PIE2, IC1IE. Assume IC1E bit is placed in PIE2 Peripheral
Interrupt Enable register in the target device. The actual IC1IF bit is written on Q2 rising edge.
5: Post decimation value is changed from PDEC = 01 (decimate by 4) to PDEC = 00 (decimate by 1).
16.2.6.2 Velocity Postscaler
The velocity event pulse (velcap, see Figure 16-12)
serves as the TMR5 capture trigger to IC1 while in the
Velocity mode. The number of velocity events are
reduced by the velocity postscaler before they are used
as the input capture clock. The velocity event reduction
ratio can be set with the PDEC1:PDEC0 control bits
(QEICON<1:0>) to 1:4, 1:16, 1:64 or no reduction (1:1).
The velocity postscaler settings are automatically
reloaded from their previous values as the Velocity
mode is re-enabled.
16.2.6.3 CAP1REN in Velocity Mode
The TMR5 value can be reset (TMR5 register pair =
0000h) on a velocity event capture by setting the
CAP1REN bit (CAP1CON<6>). When CAP1REN is
cleared, the TMR5 time base will not be reset on any
velocity event capture pulse. The VELR register pair,
however, will continue to be updated with the current
TMR5 value.
 2003 Microchip Technology Inc.
Preliminary
DS39616B-page 177