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PIC18F2331 Datasheet, PDF (323/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D | |||
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PIC18F2331/2431/4331/4431
RRNCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Rotate Right f (no carry)
[ label ] RRNCF f [,d [,a]]
0 ⤠f ⤠255
d â [0,1]
a â [0,1]
(f<n>) â dest<n-1>,
(f<0>) â dest<7>
N, Z
0100 00da ffff ffff
The contents of register âfâ are
rotated one bit to the right. If âdâ is
0, the result is placed in W. If âdâ is
1, the result is placed back in regis-
ter âfâ (default). If âaâ is 0, the Access
Bank will be selected, overriding
the BSR value. If âaâ is 1, then the
bank will be selected as per the
BSR value (default).
register f
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Decode
Read
register âfâ
Q3
Process
Data
Q4
Write to
destination
Example 1:
RRNCF REG, 1, 0
Before Instruction
REG = 1101 0111
After Instruction
REG = 1110 1011
Example 2:
RRNCF REG, W
Before Instruction
W
REG
=?
= 1101 0111
After Instruction
W
REG
= 1110 1011
= 1101 0111
SETF
Set f
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
[ label ] SETF f [,a]
0 ⤠f ⤠255
a â [0,1]
FFh â f
None
0110 100a ffff ffff
The contents of the specified
register are set to FFh. If âaâ is 0,
the Access Bank will be selected,
overriding the BSR value. If âaâ is 1,
then the bank will be selected as
per the BSR value (default).
1
1
Q Cycle Activity:
Q1
Q2
Decode
Read
register âfâ
Q3
Process
Data
Q4
Write
register âfâ
Example:
SETF
Before Instruction
REG
=
After Instruction
REG
=
REG
0x5A
0xFF
 2003 Microchip Technology Inc.
Preliminary
DS39616B-page 321
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