PIC18F2331 Datasheet, PDF (13/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
FIGURE 1-2:
PIC18F4331/4431 BLOCK DIAGRAM
Data Bus<8>
21
21
Address Latch
Program Memory
Data Latch
21 ^{Table Pointer<21>}
inc/dec logic
8
8
20
PCLATU PCLATH
PCU PCH PCL
Program Counter
31 Level Stack
Data Latch
Data RAM
(768 bytes)
Address Latch
12
Address<12>
4
12
4
BSR _{FSR0 Bank0, F}
FSR1
FSR2
12
16
TABLELATCH
Decode
inc/dec
logic
8
ROMLATCH
PORTA
PORTB
PORTC
OSC2/CLKO
OSC1/CLKI
T1OSI
T1OSO
MCLR/VPP
VDD, VSS
IR
Instruction
Decode &
Control
Timing
Generation
4X PLL
Precision
Band Gap
Reference
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Power
Managed
Mode Logic
INTRC
OSC
8
PRODH PRODL
3
8 x 8 Multiply
8
BITOP
W
8
8
8
8
ALU<8>
8
PORTD
PORTE
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CAP1/INDX
RA3/AN3/VREF+/CAP2/QEA
RA4/AN4/CAP3/QEB
RA5/AN5/LVDIN
OSC2/CLKO/RA6
OSC1/CLKI/RA7
RB0/PWM0
RB1/PWM1
RB2/PWM2
RB3/PWM3
RB4/KBI0/PWM5
RB5/KBI1/PWM4/PGM⁽⁴⁾
RB6/KBI2/PGC
RB7/KBI3/PGD
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2/FLTA⁽²⁾
RC2/CCP1/FLTB
RC3/T0CKI/T5CKI/INT0⁽³⁾
RC4/INT1/SDI/SDA⁽³⁾
RC5/INT2/SCK/SCL⁽³⁾
RC6/TX/CK/SS
RC7/RX/DT/SDO*
RD0/IT0CKI/T5CKI
RD1/SDO
RD2/SDI/SDA
RD3/SCK/SCL
RD4/FLTA⁽²⁾
RD5/PWM4⁽⁴⁾
RD6/PWM6
RD7/PWM7
RE0/AN6
RE1/AN7
RE2/AN8
MCLR/VPP/RE3⁽¹⁾
Timer0
Timer1
Timer2
Timer5
HS 10-bit
ADC
AVDD, AVSS
Data EE
CCP1
CCP2
Synchronous
Serial Port
EUSART
PCPWM
Note 1:
2:
3:
4:
RE3 is available only when MCLR is disabled.
RD4 is the alternate pin for FLTA.
RC3, RC4 and RC5 are alternate pins for T0CKI/T5CKI, SDI/SDA, SCK/SCL
respectively.
RD5 is the alternate pin for PWM4.
 2003 Microchip Technology Inc.
Preliminary
MFM
DS39616B-page 11