PIC18F2331 Datasheet, PDF (211/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
17.13 PWM Update Lockout
For a complex PWM application, the user may need to
write up to four Duty Cycle registers and the Time Base
Period Register, PTPER, at a given time. In some
applications, it is important that all buffer registers be
written before the new duty cycle and period values are
loaded for use by the module.
A PWM update lockout feature may optionally be
enabled so the user may specify when new duty cycle
buffer values are valid. The PWM update lockout
feature is enabled by setting the control bit UDIS in the
PWMCON1 register. This bit affects all Duty Cycle
Buffer registers and the PWM time base period buffer,
PTPER.
To perform a PWM update lockout:
1. Set the UDIS bit.
2. Write all Duty Cycle registers and PTPER, if
applicable.
3. Clear the UDIS bit to re-enable updates.
4. With this, when UDIS bit is cleared, the buffer
values will be loaded to the actual registers. This
makes a synchronous loading of the registers.
17.14 PWM Special Event Trigger
The PWM module has a special event trigger capability
that allows A/D conversions to be synchronized to the
PWM time base. The A/D sampling and conversion
time may be programmed to occur at any point within
the PWM period. The special event trigger allows the
user to minimize the delay between the time when A/D
conversion results are acquired and the time when the
duty cycle value is updated.
The PWM 16-bit Special Event Trigger register
SEVTCMP (high and low), and five control bits in
PWMCON1 register are used to control its operation.
The PTMR value for which a special event trigger
should occur is loaded into the SEVTCMP register pair.
SEVTDIR bit in PWMCON1 register specifies the
counting phase when the PWM time base is in an
Up/Down Counting mode.
If the SEVTDIR bit is cleared, the special event trigger
will occur on the upward counting cycle of the PWM
time base. If SEVTDIR is set, the special event trigger
will occur on the downward count cycle of the PWM
time base. The SEVTDIR bit has effect only when PWM
timer is in the Up/Down Counting mode.
17.14.1 SPECIAL EVENT TRIGGER ENABLE
The PWM module will always produce special event
trigger pulses. This signal may optionally be used by
the A/D module. Refer to Chapter 20.0 "10-bit
High-Speed Analog-to-Digital Converter (A/D)
Module" for details.
17.14.2 SPECIAL EVENT TRIGGER
POSTSCALER
The PWM special event trigger has a postscaler that
allows a 1:1 to 1:16 postscale ratio. The postscaler is
configured by writing the SEVOPS3:SEVOPS0 control
bits in the PWMCON1 register.
The special event output postscaler is cleared on any
write to the SEVTCMP register pair, or on any device
Reset.
 2003 Microchip Technology Inc.
Preliminary
DS39616B-page 209