PIC18F2331 Datasheet, PDF (260/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
20.9.1 A/D RESULT REGISTER
The ADRESH:ADRESL register pair is the location
where the 10-bit A/D result is loaded at the completion
of the A/D conversion. This register pair is 16-bits wide.
The A/D module gives the flexibility to left- or right-
justify the 10-bit result in the 16-bit result register. The
FIGURE 20-5:
A/D RESULT JUSTIFICATION
A/D Format Select bit (ADFM) controls this justification.
Figure 20-5 shows the operation of the A/D result
justification. The extra bits are loaded with ‘0’s. When
an A/D result will not overwrite these locations (A/D
disable), these registers may be used as two general
purpose 8-bit registers.
10-bit Result
ADFM = 1
ADFM = 0
7
2107
0
0000 00
ADRESH
ADRESL
10-bit Result
Right Justified
7
0765
0
0000 00
ADRESH
ADRESL
10-bit Result
Left Justified
EQUATION 20-3: CONVERSION TIME FOR MULTICHANNEL MODES
Sequential Mode:
T = (TACQ)_A + (TCON)_A + [(TACQ)_B - 12TAD] + (TCON)_B + [(TACQ)_C - 12TAD] + (TCON)_C + [(TACQ)_D - 12TAD] + (TCON)_D
Simultaneous Mode:
T = TACQ + (TCON)_A + (TCON)_B + TACQ + (TCON)_C + (TCON)_D
DS39616B-page 258
Preliminary
 2003 Microchip Technology Inc.