PIC18F2331 Datasheet, PDF (197/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
17.6 PWM Duty Cycle
PWM duty cycle is defined by PDCx (PDCxL and
PDCxH) registers. There are a total of 4 PWM Duty
Cycle registers for 4 pairs of PWM channels. The Duty
Cycle registers have 14-bit resolution by combining
6 LSbs of PDCxH with the 8 bits of PDCxL. PDCx is a
double-buffered register used to set the counting
period for the PWM time base.
17.6.1 PWM DUTY CYCLE REGISTERS
There are four 14-bit special function registers used to
specify duty cycle values for the PWM module:
• PDC0 (PDC0L and PDC0H)
• PDC1 (PDC1L and PDC1H)
• PDC2 (PDC2L and PDC2H)
• PDC3 (PDC3L and PDC3H)
FIGURE 17-11:
DUTY CYCLE COMPARISON
PTMRH<7:0>
The value in each Duty Cycle register determines the
amount of time that the PWM output is in the active
state. The upper 12 bits of PDCn hold the actual duty
cycle value from PTMRH/L<11:0>, while the lower 2
bits control which internal Q-clock the duty cycle match
occurs. This 2-bit value is decoded from the Q-clocks
as shown in Figure 17-11 (when the prescaler is 1:1
(PTCKPS = 00)).
In Edge-aligned mode, the PWM period starts at Q1
and ends when the Duty Cycle register matches the
PTMR register as follows. The duty cycle match is con-
sidered when the upper 12 bits of the PDC is equal to
the PTMR and the lower 2 bits are equal to Q1, Q2, Q3
or Q4, depending on the lower two bits of the PDC
(when the prescaler is 1:1, or PTCKPS = 00).
Note:
When prescaler is not 1:1 (PTCKPS ≠
~00), the duty cycle match occurs at Q1
clock of the instruction cycle when the
PTMR and PDC match occurs.
Each compare unit has logic that allows override of the
PWM signals. This logic also ensures that the PWM
signals will complement each other (with dead time
insertion) in Complementary mode (see Section 17.7
“Dead Time Generators”).
PTMRL<7:0>
PTMR<11:0>
PDCn<13:0>
UNUSED
PTMRH<3:0>
PTMRL<7:0>
Q-CLOCKS⁽¹⁾
<1:0>
UNUSED
COMPARATOR
PDCnH<5:0>
PDCnL<7:0>
PDCnH<7:0>
Note 1: This value is decoded from the Q-Clocks:
00 = duty cycle match occurs on Q1
01 = duty cycle match occurs on Q2
10 = duty cycle match occurs on Q3
11 = duty cycle match occurs on Q4
PDCnL<7:0>
 2003 Microchip Technology Inc.
Preliminary
DS39616B-page 195