PIC18F2331 Datasheet, PDF (156/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
15.4 Compare Mode
In Compare mode, the 16-bit CCPR1 (CCPR2) register
value is constantly compared against the TMR1
register pair value. When a match occurs, the RC2/
CCP1 (RC1/CCP2) pin:
• Is driven High
• Is driven Low
• Toggles output (High-to-Low or Low-to-High)
• Remains unchanged (interrupt only)
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP2M3:CCP2M0). At the
same time, interrupt flag bit CCP1IF (CCP2IF) is set.
15.4.1 CCP PIN CONFIGURATION
The user must configure the CCPx pin as an output by
clearing the appropriate TRISC bit.
Note:
Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to
the default low level. This is not the
PORTC I/O data latch.
15.4.2 TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
15.4.3 SOFTWARE INTERRUPT MODE
When generate software interrupt is chosen, the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
15.4.4 SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
The special trigger output of CCP2 resets the TMR1
register pair. Additionally, the CCP2 special event
trigger will start an A/D conversion if the A/D module is
enabled.
Note:
The special event trigger from the CCP2
module will not set the Timer1 interrupt
flag bit.
FIGURE 15-2:
COMPARE MODE OPERATION BLOCK DIAGRAM
Special Event Trigger will:
Reset Timer1, but not set Timer1 interrupt flag bit,
and set bit GO/DONE (ADCON0<2>), which starts an A/D conversion (CCP2 only)
Special Event Trigger
Set Flag bit CCP1IF
RC2/CCP1 pin
TRISC<2>
Output Enable
QS
R
Output
Logic
CCP1CON<3:0>
Mode Select
Match
CCPR1H CCPR1L
Comparator
Special Event Trigger
Set Flag bit CCP2IF
RC1/CCP2 pin
TRISC<1>
Output Enable
QS
R
Output
Logic
CCP2CON<3:0>
Mode Select
Match
TMR1H TMR1L
Comparator
CCPR2H CCPR2L
DS39616B-page 154
Preliminary
 2003 Microchip Technology Inc.