PIC18F2331 Datasheet, PDF (109/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
10.0 I/O PORTS
Depending on the device selected and features
enabled, there are up to five ports available. Some pins
of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
Each port has three registers for its operation. These
registers are:
• TRIS register (data direction register)
• PORT register (reads the levels on the pins of the
device)
• LAT register (output latch)
The data latch (LAT register) is useful for read-modify-
write operations on the value that the I/O pins are
driving.
A simplified model of a generic I/O port without the
interfaces to other peripherals is shown in Figure 10-1.
FIGURE 10-1:
GENERIC I/O PORT
OPERATION
RD LAT
Data
Bus
WR LAT
or PORT
WR TRIS
RD TRIS
D
Q
CK
Data Latch
DQ
CK
TRIS Latch
I/O pin⁽¹⁾
Input
Buffer
Q
D
RD PORT
ENEN
Note 1: I/O pins have diode protection to VDD and VSS.
10.1 PORTA, TRISA and LATA
Registers
PORTA is a 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
High-Impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, whereas writing to it, will write to the port latch.
The Data Latch register (LATA) is also memory mapped.
Read-modify-write operations on the LATA register read
and write the latched output value for PORTA.
The RA<2:4> pins are multiplexed with three input
capture pins and Quadrature Encoder Interface pins.
Pins RA6 and RA7 are multiplexed with the main
oscillator pins; they are enabled as oscillator or I/O pins
by the selection of the main oscillator in Configuration
Register 1H (see Section 22.1 “Configuration Bits”
for details). When they are not used as port pins, RA6
and RA7 and their associated TRIS and LAT bits are
read as ‘0’.
The other PORTA pins are multiplexed with analog
inputs, the analog VREF+ and VREF- inputs and the com-
parator voltage reference output. The operation of pins
RA3:RA0 and RA5 as A/D converter inputs is selected
by clearing/setting the control bits in the ANSEL0 and
ANSEL1 registers.
Note 1: On a Power-on Reset, RA5:RA0 are con-
figured as analog inputs and read as ‘0’.
2: RA5 I/F is available only on 40-pin
devices (PIC18F4X31).
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
EXAMPLE 10-1: INITIALIZING PORTA
CLRF
CLRF
MOVLW
MOVWF
MOVLW
MOVWF
PORTA
LATA
0x3F
ANSEL0
0xCF
TRISA
; Initialize PORTA by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Configure A/D
; for digital inputs
; Value used to
; initialize data
; direction
; Set RA<3:0> as inputs
; RA<5:4> as outputs
 2003 Microchip Technology Inc.
Preliminary
DS39616B-page 107