PIC18F2331 Datasheet, PDF (292/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
TABLE 23-2: PIC18FXXX INSTRUCTION SET
Mnemonic,
Operands
Description
16-Bit Instruction Word
Cycles
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ADDWFC
ANDWF
CLRF
COMF
CPFSEQ
CPFSGT
CPFSLT
DECF
DECFSZ
DCFSNZ
INCF
INCFSZ
INFSNZ
IORWF
MOVF
MOVFF
MOVWF
MULWF
NEGF
RLCF
RLNCF
RRCF
RRNCF
SETF
SUBFWB
SUBWF
SUBWFB
SWAPF
TSTFSZ
XORWF
f, d, a
f, d, a
f, d, a
f, a
f, d, a
f, a
f, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f_s, f_d
f, a
f, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, a
f, d, a
Add WREG and f
1
0010
Add WREG and Carry bit to f 1
0010
AND WREG with f
1
0001
Clear f
1
0110
Complement f
1
0001
Compare f with WREG, skip = 1 (2 or 3) 0110
Compare f with WREG, skip > 1 (2 or 3) 0110
Compare f with WREG, skip < 1 (2 or 3) 0110
Decrement f
1
0000
Decrement f, Skip if 0
1 (2 or 3) 0010
Decrement f, Skip if Not 0
1 (2 or 3) 0100
Increment f
1
0010
Increment f, Skip if 0
1 (2 or 3) 0011
Increment f, Skip if Not 0
1 (2 or 3) 0100
Inclusive OR WREG with f 1
0001
Move f
1
0101
Move f_s (source) to 1st word 2
f_d (destination) 2nd word
Move WREG to f
1
1100
1111
0110
Multiply WREG with f
1
0000
Negate f
1
0110
Rotate Left f through Carry 1
0011
Rotate Left f (No Carry)
1
0100
Rotate Right f through Carry 1
0011
Rotate Right f (No Carry)
1
0100
Set f
1
0110
Subtract f from WREG with 1
0101
borrow
Subtract WREG from f
1
0101
Subtract WREG from f with 1
0101
borrow
Swap nibbles in f
1
0011
Test f, skip if 0
1 (2 or 3) 0110
Exclusive OR WREG with f 1
0001
01da
00da
01da
101a
11da
001a
010a
000a
01da
11da
11da
10da
11da
10da
00da
00da
ffff
ffff
111a
001a
110a
01da
01da
00da
00da
100a
01da
11da
10da
10da
011a
10da
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff C, DC, Z, OV, N 1, 2
ffff C, DC, Z, OV, N 1, 2
ffff Z, N
1,2
ffff Z
2
ffff Z, N
1, 2
ffff None
4
ffff None
4
ffff None
1, 2
ffff C, DC, Z, OV, N 1, 2, 3, 4
ffff None
1, 2, 3, 4
ffff None
1, 2
ffff C, DC, Z, OV, N 1, 2, 3, 4
ffff None
4
ffff None
1, 2
ffff Z, N
1, 2
ffff Z, N
1
ffff None
ffff
ffff None
ffff None
ffff C, DC, Z, OV, N 1, 2
ffff C, Z, N
ffff Z, N
1, 2
ffff C, Z, N
ffff Z, N
ffff None
ffff C, DC, Z, OV, N 1, 2
ffff C, DC, Z, OV, N
ffff C, DC, Z, OV, N 1, 2
ffff None
4
ffff None
1, 2
ffff Z, N
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
f, b, a Bit Clear f
1
1001 bbba ffff ffff None
1, 2
BSF
f, b, a Bit Set f
1
1000 bbba ffff ffff None
1, 2
BTFSC f, b, a Bit Test f, Skip if Clear
1 (2 or 3) 1011 bbba ffff ffff None
3, 4
BTFSS f, b, a Bit Test f, Skip if Set
1 (2 or 3) 1010 bbba ffff ffff None
3, 4
BTG
f, d, a Bit Toggle f
1
0111 bbba ffff ffff None
1, 2
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be
that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and
is driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared
if assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP,
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that
all program memory locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
DS39616B-page 290
Preliminary
 2003 Microchip Technology Inc.