PIC18F2331 Datasheet, PDF (150/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
14.5 Timer5 Interrupt
Timer5 has the ability to generate an interrupt on a
period match. When the PR5 register is loaded with a
new period value (00FFh), the Timer5 time base incre-
ments until its value is equal to the value of PR5. When
a match occurs, the Timer5 interrupt is generated on
the rising edge of Q4; TMR5IF is set on the next TCY.
The interrupt latency (i.e., the time elapsed from the
moment Timer5 rolls over until TMR5IF is set) will not
exceed 1 TCY. When the Timer5 clock input is
prescaled and a TMR5/PR5 match occurs, the interrupt
will be generated on the first Q4 rising edge after TMR5
resets.
14.6 Timer5 Special Event Trigger
Output
A Timer5 special event trigger is generated on a TMR5/
PR5 match. The special event trigger is generated on
the falling edge of Q3.
Timer5 must be configured for either Synchronous
mode (counter or timer) to take advantage of the
special event trigger feature. If Timer5 is running in
Asynchronous Counter mode, the special event trigger
may not work and should not be used.
14.7 Timer5 Special Event Reset Input
In addition to the special event output, Timer5 has a
Special Event Reset input that may be used with Input
Capture channel 1 (IC1) of the Motion Feedback
module. To use the Special Event Reset, the Capture 1
Control register CAP1CON must be configured for one
of the special event trigger modes (CAP1M3:CAP1M0
= 1110 or 1111). The Special Event Reset trigger can
be disabled by setting the RESEN control bit
(T5CON<6>).
The Special Event Reset resets the Timer5 time base.
This reset occurs in either Continuous-count or Single-
shot modes.
14.7.1 WAKE-UP ON IC1 EDGE
The Timer5 Special Event Reset input can act as a
Timer5 wake-up and a start-up pulse. Timer5 must be
in Single-shot mode and disabled (TMR5ON = 0). An
active edge on the CAP1 input pin will set TMR5ON;
the timer is subsequently incremented on the next fol-
lowing clock according to the prescaler and the Timer5
clock settings. A subsequent hardware time-out (such
as TMR5/PR5 match) will clear the TMR5ON bit and
stop the timer.
14.7.2 DELAYED-ACTION EVENT
TRIGGER
An active edge on CAP1 can also be used to initiate
some later action delayed by the Timer5 time base. In
this case, Timer5 increments as before after being
triggered. When the hardware time-out occurs, the
special event trigger output is generated and used to
trigger another action, such as an A/D conversion. This
allows a given hardware action to be referenced from a
capture edge on CAP1 and delayed by the timer.
The event timing for the delayed action event trigger is
discussed further in Section 16.1 “Input Capture”.
14.7.3 SPECIAL EVENT RESET WHILE
TIMER5 IS INCREMENTING
In the event that a bus write to Timer5 coincides with a
Special Event Reset trigger, the bus write will always
take precedence over Special Event Reset trigger.
14.8 Operation in Sleep Mode
When Timer5 is configured for asynchronous opera-
tion, it will continue to increment each timer clock (or
prescale multiple of clocks). Executing the SLEEP
instruction will either stop the timer or let the timer con-
tinue, depending on the setting of the Timer5 Sleep
Enable bit, T5SE. If T5SE is set (= 1), the timer contin-
ues to run when the SLEEP instruction is executed and
the external clock is selected (TMR5CS = 1). If T5SE is
cleared, the timer stops when a SLEEP instruction is
executed, regardless of the state of the GTPCS bit.
To summarize, Timer5 will continue to increment when
a SLEEP instruction is executed only if all of these bits
are set:
• TMR5ON
• T5SE
• TMR5CS
• T5SYNC
14.8.1 INTERRUPT DETECT IN SLEEP
MODE
When configured as described above, Timer5 will
continue to increment on each rising edge on T5CKI
while in Sleep mode. When a TMR5/PR5 match
occurs, an interrupt is generated which can wake the
part.
DS39616B-page 148
Preliminary
 2003 Microchip Technology Inc.