PIC18F2331 Datasheet, PDF (365/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
FIGURE 25-13: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
70
71
72
83
78
79
80
79
78
SDO
MSb
bit6 - - - - - -1
LSb
SDI
Note:
75, 76
MSb IN
bit6 - - - -1
74
73
Refer to Figure 25-4 for load conditions.
77
LSb IN
TABLE 25-13: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0))
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TssL2scH, SS↓ to SCK↓ or SCK↑ input
TssL2scL
TCY
—
71
TscH
71A
SCK input high time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
72
TscL
72A
SCK input low time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
73
TdiV2scH, Setup time of SDI data input to SCK edge
TdiV2scL
100
—
73A TB2B
Last clock edge of Byte1 to the first clock edge of Byte2 1.5 TCY + 40 —
74
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
100
—
75
TdoR
SDO data output rise time
PIC18FXX31
—
25
PIC18LFXX31
45
76
TdoF
SDO data output fall time
—
25
77
TssH2doZ SS↑ to SDO output hi-impedance
10
50
78
TscR
SCK output rise time (Master mode) PIC18FXX31
—
25
PIC18LFXX31
45
79
TscF
SCK output fall time (Master mode)
—
25
80
TscH2doV, SDO data output valid after SCK edge PIC18FXX31
—
50
TscL2doV
PIC18LFXX31
100
83
TscH2ssH, SS ↑ after SCK edge
TscL2ssH
1.5 TCY + 40 —
Note 1: Requires the use of Parameter # 73A.
2: Only if Parameter # 71A and # 72A are used.
ns
ns
ns (Note 1)
ns
ns (Note 1)
ns
ns (Note 2)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
 2003 Microchip Technology Inc.
Preliminary
DS39616B-page 363