PIC18F2331 Datasheet, PDF (298/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
BCF
Bit Clear f
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
[ label ] BCF
0 ≤ f ≤ 255
0≤b≤7
a ∈ [0,1]
0 → f<b>
None
f,b[,a]
1001 bbba ffff ffff
Bit ‘b’ in register ‘f’ is cleared. If ‘a’
is 0, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Decode
Read
register ‘f’
Q3
Process
Data
Q4
Write
register ‘f’
Example:
BCF
FLAG_REG, 7
Before Instruction
FLAG_REG = 0xC7
After Instruction
FLAG_REG = 0x47
BN
Branch if Negative
Syntax:
[ label ] BN n
Operands:
-128 ≤ n ≤ 127
Operation:
if negative bit is ‘1’
(PC) + 2 + 2n → PC
Status Affected: None
Encoding:
1110 0110 nnnn nnnn
Description:
If the Negative bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then a
two-cycle instruction.
Words:
1
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
No
operation
If No Jump:
Read literal
‘n’
No
operation
Process
Data
No
operation
Write to PC
No
operation
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
Before Instruction
PC
=
After Instruction
If Negative =
PC
=
If Negative =
PC
=
BN Jump
address (HERE)
1;
address (Jump)
0;
address (HERE+2)
DS39616B-page 296
Preliminary
 2003 Microchip Technology Inc.