PIC18F2331 Datasheet, PDF (173/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
16.2.1 QEI CONFIGURATION
The QEI module shares its input pins with the Input
Capture module. The inputs are mutually exclusive;
only the IC module or the QEI module (but not both)
can be enabled at one time. Also, because the IC and
QEI are multiplexed to the same input pins, the
programmable noise filters can be dedicated to one
module only.
The operation of the QEI is controlled by the QEICON
configuration register. See Register 16-2.
Note:
In the event that both QEI and IC are
enabled, QEI will take precedence and IC
will remain disabled.
REGISTER 16-2:
QEICON: QUADRATURE ENCODER INTERFACE CONTROL REGISTER
R/W-0 R/W-0
R-0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
VELM ERROR UP/DOWN QEIM2 QEIM1 QEIM0 PDEC1 PDEC0
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4-2
bit 1-0
VELM: Velocity Mode bit
1 = Velocity mode disabled
0 = Velocity mode enabled
ERROR: QEI error bit⁽¹⁾
1 = Position counter⁽⁴⁾ overflow or underflow
0 = No overflow or underflow
UP/DOWN: Direction of Rotation Status bit⁽¹⁾
1 = Forward
0 = Reverse
QEIM2:QEIM0: QEI Mode bits^(2,3)
111 =Unused
110 =QEI enabled in 4x Update mode; position counter reset on period match
(POSCNT = MAXCNT)
101 =QEI enabled in 4x Update mode; INDX resets the position counter
100 =Unused
010 =QEI enabled in 2x Update mode; position counter reset on period match
(POSCNT = MAXCNT)
001 =QEI enabled in 2x Update mode; INDX resets the position counter
000 =QEI off
PDEC1:PDEC0: Velocity Pulse Reduction Ratio bit
11 =1:64
10 =1:16
01 =1:4
00 =1:1
Note 1: QEI must be enabled and in Index mode.
2: QEI mode select must be cleared (= 000) to enable CAP1, CAP2 or CAP3 inputs. If QEI and
IC modules are both enabled, QEI will take precedence.
3: Enabling one of the QEI operating modes remaps the IC buffer registers CAP1BUFH,
CAP1BUFL, CAP2BUFH, CAP2BUFL, CAP3BUFH and CAP3BUFL as the VREGH,
VREGL, POSCNTH, POSCNTL, MAXCNTH, and MAXCNTL registers (respectively) for the
QEI.
4: ERROR bit must be cleared in software.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = bit is cleared x = bit is unknown
 2003 Microchip Technology Inc.
Preliminary
DS39616B-page 171