PIC18F2331 Datasheet, PDF (149/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
the Timer5 is incremented on the next Q1. The T5CKI
minimum pulse width high and low time must be
greater than TCY/2.
In Asynchronous Counter configuration, Timer5 is
clocked by the external clock (T5CKI) with the optional
prescaler. In this mode, T5CKI is not synchronized to
the internal clock. By setting TMR5CS, the external
input clock (T5CKI) can be used as the counter sam-
pling clock. When T5SYNC is set, the external clock is
not synchronized to the internal device clock.
The timer count is not reset automatically when the
module is disabled. The user may write the counter
register to initialize the counter.
Note:
The Timer5 module does NOT prevent
writes to the PR5 registers (PR5H:PR5L)
while the timer is enabled. Writing to PR5
while the timer is enabled may result in
unexpected period match events.
14.1.1 CONTINUOUS AND SINGLE-SHOT
OPERATION
Timer5 has two operating modes: Continuous-count
and Single-shot.
Continuous-count mode is selected by clearing the
T5MOD control bit (= 0). In this mode, the Timer5 time
base will start incrementing according to the prescaler
settings until a TMR5/PR5 match occurs, or until TMR5
rolls over (FFFFh to 0000h). The TMR5IF interrupt flag
is set, the TMR5 register is reset on the following input
clock edge, and the timer continues to count for as long
as the TMR5ON bit remains set.
Single-shot mode is selected by setting T5MOD (= 1).
In this mode, the Timer5 time base begins to increment
according to the prescaler settings until a TMR5/PR5
match occurs. This causes the TMR5IF interrupt flag to
be set, the TMR5 register pair to be cleared on the
following input clock edge, and the TMR5ON bit to be
cleared by the hardware to halt the timer.
The Timer5 time base can only start incrementing in
Single-shot mode under two conditions:
1. Timer5 is enabled (TMR5ON is set), or
2. Timer5 is disabled, and a Special Event Reset
trigger is present on the Timer5 reset input. (See
Section 14.7 “Timer5 Special Event Reset
Input” for additional information).
14.2 16-bit Read/Write and Write Modes
As noted, the actual high byte of the Timer5 register
pair is mapped to TMR5H, which serves as a buffer.
Reading TMR5L will load the contents of the high byte
of the register pair into the TMR5H register. This allows
the user to accurately read all 16 bits of the register
pair, without having to determine whether a read of the
high byte followed by the low byte is valid due to a
rollover between reads.
Since the actual high byte of the Timer5 register pair is
not directly readable or writable, it must be read and
written to through the Timer5 High Byte Buffer register
(TMR5H). The T5 high byte is updated with the con-
tents of TMR5H when a write occurs to TMR5L. This
allows a user to write all 16 bits to both the high and low
bytes of Timer5 at once. Writes to TMR5H do not clear
the Timer5 prescaler. The prescaler is only cleared on
writes to TMR5L.
14.2.1 16-BIT READ-MODIFY-WRITE
Read-modify-write instructions like BSF and BCF will
read the contents of a register, make the appropriate
changes, and place the result back into the register.
The write portion of a read-modify-write instruction of
TMR5H will not update the contents of the high byte of
TMR5 until a write of TMR5L takes place. Only then will
the contents of TMR5H be placed into the high byte of
TMR5.
14.3 Timer5 Prescaler
The Timer5 clock input (either TCY or the external clock)
may be divided by using the Timer5 programmable
prescaler. The prescaler control bits T5PS1:T5PS0
(T5CON<4:3>) select a prescale factor of 2, 4, 8 or no
prescale.
The Timer5 prescaler is cleared by any of the following:
• A write to the Timer5 register
• Disabling Timer5 (TMR5ON = 0)
• A device Reset such as Master Clear, POR or
BOR
Note: Writing to the T5CON register does not
clear the Timer5.
14.4 Noise Filter
The Timer5 module includes an optional input noise
filter, designed to reduce spurious signals in noisy
operating environments. The filter ensures that the
input is not permitted to change until a stable value has
been registered for three consecutive sampling clock
cycles.
The noise filter is part of the input filter network associ-
ated with the Motion Feedback Module (see
Section 16.0 “Motion Feedback Module”). All of the
filters are controlled using the Digital Filter Control
(DFLTCON) register (Register 16-3). The Timer5 filter
can be individually enabled or disabled by setting or
clearing the FLT4EN bit (DFLTCON<7>). It is disabled
on all BOR and BOR resets.
For additional information, refer to Section 16.3
“Noise Filters” in the Motion Feedback module.
 2003 Microchip Technology Inc.
Preliminary
DS39616B-page 147