PIC18F2331 Datasheet, PDF (108/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
9.6 INTn Pin Interrupts
External interrupts on the RC3/INT0, RC4/INT1 and
RC5/INT2 pins are edge triggered: either rising, if the
corresponding INTEDGx bit is set in the INTCON2
register, or falling, if the INTEDGx bit is clear. When a
valid edge appears on the RC3/INT0 pin, the
corresponding flag bit INTxF is set. This interrupt can
be disabled by clearing the corresponding enable bit
INTxE. Flag bit INTxF must be cleared in software in
the interrupt service routine before re-enabling the
interrupt. All external interrupts (INT0, INT1 and INT2)
can wake-up the processor from the power-managed
modes, if bit INTxE was set prior to going into power-
managed modes. If the global interrupt enable bit GIE
is set, the processor will branch to the interrupt vector
following wake-up.
Interrupt priority for INT1 and INT2 is determined by the
value contained in the interrupt priority bits, INT1IP
(INTCON3<6>) and INT2IP (INTCON3<7>). There is
no priority bit associated with INT0. It is always a high
priority interrupt source.
9.7 TMR0 Interrupt
In 8-bit mode (which is the default), an overflow
(FFh → 00h) in the TMR0 register will set flag bit
TMR0IF. In 16-bit mode, an overflow (FFFFh → 0000h)
in the TMR0H:TMR0L registers will set flag bit TMR0IF.
The interrupt can be enabled/disabled by setting/clear-
ing enable bit TMR0IE (INTCON<5>). Interrupt priority
for Timer0 is determined by the value contained in the
interrupt priority bit TMR0IP (INTCON2<2>). See
Section 11.0 “Timer0 Module” for further details.
9.8 PORTB Interrupt-on-Change
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON<3>).
Interrupt priority for PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RBIP (INTCON2<0>).
9.9 Context Saving During Interrupts
During interrupts, the return PC address is saved on
the stack. Additionally, the WREG, Status and BSR
registers are saved on the fast return stack. If a fast
return from interrupt is not used (See Section 5.3
“Fast Register Stack”), the user may need to save the
WREG, Status and BSR registers on entry to the
interrupt service routine. Depending on the user’s
application, other registers may also need to be saved.
Example 9-1 saves and restores the WREG, Status
and BSR registers during an interrupt service routine.
EXAMPLE 9-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF W_TEMP
MOVFF STATUS,STATUS_TEMP
MOVFF BSR,BSR_TEMP
;
; USER ISR CODE
;
MOVFF BSR_TEMP,BSR
MOVF W_TEMP, W
MOVFF STATUS_TEMP, STATUS
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR_TMEP located anywhere
; Restore BSR
; Restore WREG
; Restore STATUS
DS39616B-page 106
Preliminary
 2003 Microchip Technology Inc.