PIC18F2331 Datasheet, PDF (71/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2331/2431/4331/4431) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details on
POR, BOR page:
PTPERL
PWM Time Base Period register (Lower 8 bits).
1111 1111
184
PTPERH
UNUSED
PWM Time Base Period register (Upper 4 bits) ---- 1111
184
PDC0L
PWM Duty Cycle #0L register (Lower 8 bits)
--00 0000
184
PDC0H
UNUSED
PWM Duty Cycle #0H register (Upper 6 bits)
0000 0000
184
PDC1L
PWM Duty Cycle #1L register (Lower 8 bits)
0000 0000
184
PDC1H
UNUSED
PWM Duty Cycle #1H register (Upper 6 bits)
--00 0000
184
PDC2L
PWM Duty Cycle #2L register (Lower 8 bits)
0000 0000
184
PDC2H
UNUSED
PWM Duty Cycle #2H register (Upper 6 bits)
--00 0000
184
PDC3L
PWM Duty Cycle #3L register (Lower 8 bits)
0000 0000
184
PDC3H
UNUSED
PWM Duty Cycle #3H register (Upper 6 bits)
--00 0000
184
SEVTCMPL PWM Special Event Compare register (Lower 8 bits)
0000 0000
N/A
SEVTCMPH
UNUSED
PWM Special Event Compare reg (Upper 4 bits) ---- 0000
N/A
PWMCON0
—
PWMEN2 PWMEN1 PWMEN0 PMOD3
PMOD2
PMOD1
PMOD0 -101 0000 _{52, 187}
PWMCON1 SEVOPS3 SEVOPS2 SEVOPS1 SEVOPS0 SEVTDIR
—
UDIS
OSYNC 0000 0-00 _{52, 188}
DTCON
DTPS1
DTPS0
DT5
DT4
DT3
DT2
DT1
DT0
0000 0000 _{52, 200}
FLTCONFIG
—
FLTBS FLTBMOD FLTBEN FLTCON
FLTAS FLTAMOD FLTAEN -000 0000 _{52, 208}
OVDCOND
POVD7
POVD6
POVD5
POVD4
POVD3
POVD2
POVD1
POVD0 1111 1111 _{52, 203}
OVDCONS
POUT7
POUT6
POUT5
POUT4
POUT3
POUT2
POUT1
POUT0 0000 0000 _{52, 204}
CAP1BUFH/ Capture 1 register, High Byte/
VELRH
Velocity register, High Byte
xxxx xxxx
52,
CAP1BUFL/ Capture 1 register Low Byte/
VELRL
Velocity register, Low Byte
xxxx xxxx
52
CAP2BUFH/ Capture 2 register, High Byte/
POSCNTH QEI Position Counter register, High Byte
xxxx xxxx
52
CAP2BUFL/ Capture 2 Reg., Low Byte/
POSCNTL QEI Position Counter register, Low Byte
xxxx xxxx
52
CAP3BUFH/ Capture 3 Reg., High Byte/
MAXCNTH QEI Max. Count Limit register, High Byte
xxxx xxxx
53
CAP3BUFL/ Capture 3 Reg., Low Byte/
MAXCNTL QEI Max. Count Limit register, Low Byte
xxxx xxxx
53
CAP1CON
—
CAP1REN
—
—
CAP1M3 CAP1M2 CAP1M1 CAP1M0 -0-0 0000 _{53, 163}
CAP2CON
—
CAP2REN
—
—
CAP2M3 CAP2M2 CAP2M1 CAP2M0 -0-0 0000 _{53, 163}
CAP3CON
—
CAP3REN
—
—
CAP3M3 CAP3M2 CAP3M1 CAP3M0 -0-0 0000 _{53, 163}
DFLTCON
—
FLT4EN FLT3EN FLT2EN FLT1EN FLTCK2 FLTCK1 FLTCK0 -000 0000 _{53, 178}
Legend:
Note 1:
2:
3:
4:
5:
6:
x = unknown, u = unchanged, – = unimplemented, q = value depends on condition
RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator mode only, and read
‘0’ in all other oscillator modes.
RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other modes.
Bit 21 of the PC is only available in Test mode and serial programming modes.
If PBADEN = 0, PORTB<4:0> are configured as digital input and read unknown, and if PBADEN = 1, PORTB<4:0> are configured as
analog input and read ‘0’ following a Reset.
These registers and/or bits are not implemented on the PIC18F2X31 devices, and read as ‘0’.
The RE3 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’. Otherwise, RE3 reads ‘0’. This bit is read-only.
 2003 Microchip Technology Inc.
Preliminary
DS39616B-page 69