PIC18F2331 Datasheet, PDF (170/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
FIGURE 16-7:
CAPXIF INTERRUPTS AND IC1 SPECIAL EVENT TRIGGER
OSC
CAP1 pin
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
IC1IF
TMR5 Reset
TMR5
TMR5ON⁽¹⁾
XXXX
0000
0001
Note 1:
Timer5 is only reset and enabled (assuming: TMR5ON = 0 and TMR5MOD = 1) when the Special Event Reset Trigger
is enabled for the Timer5 Reset input. TMR5ON bit is asserted and Timer5 is reset on the Q1 rising edge following the
event capture. With the Special Event Reset Trigger disabled, Timer5 cannot be reset by the Special Event Reset
Trigger on CAP1 input. In order for the Special Event Reset Trigger to work as the Reset trigger to Timer5, IC1 must be
configured in the Special Event Trigger mode (CAP1M<3:0> = 1110 or 1111).
16.1.8 SPECIAL EVENT TRIGGER (CAP1
ONLY)
The Special Event Trigger mode of IC1
(CAP1M3:CAP1M0 = 1110 or 1111) enables the
Special Event Trigger signal. The trigger signal can be
used as the Special Event Reset input to TMR5,
resetting the timer when the specific event happens on
IC1. The events are summarized in Table 16-2.
TABLE 16-2: SPECIAL EVENT TRIGGER
CAP1M3:
CAP1M0
Description
1110
1111
The trigger occurs on every falling
edge on CAP1 input
The trigger occurs on every rising
edge on CAP1 input
16.1.9 OPERATING MODES SUMMARY
Table 16-3 shows a summary of the input capture con-
figuration when used in conjunction with TMR5 timer
resource.
16.1.10 OTHER OPERATING MODES
Although the IC and QEI submodules are mutually
exclusive, the IC can be reconfigured to work with the
QEI module to perform specific functions. In effect, the
QEI “borrows” hardware from the IC to perform these
operations.
For velocity measurement, the QEI uses dedicated
hardware in channel IC1. The CAP1BUF registers are
remapped, becoming the VREG registers. Its operation
and use are described in Section 16.2.6 “Velocity
Measurement”.
While in QEI mode, the CAP2BUF and CAP3BUF reg-
isters of channel IC2 and IC3 are used for position
determination. They are remapped as the POSCNT
and MAXCNT buffer registers, respectively.
DS39616B-page 168
Preliminary
 2003 Microchip Technology Inc.