PIC18F2331 Datasheet, PDF (280/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
22.2 Watchdog Timer (WDT)
For PIC18F2331/2431/4331/4431 devices, the WDT is
driven by the INTRC source. When the WDT is
enabled, the clock source is also enabled. The nominal
WDT period is 4 ms and has the same stability as the
INTRC oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexer, controlled by bits in
Configuration Register 2H (see Register 22-3).
Available periods range from 4 ms to 131.072 seconds
(2.18 minutes). The WDT and postscaler are cleared
when any of the following events occur: execute a
SLEEP or CLRWDT instruction, the IRCF bits
(OSCCON<6:4>) are changed, or a clock failure has
occurred (see Section 22.4.1 “FSCM and the
Watchdog Timer”).
Adjustments to the internal oscillator clock period using
the OSCTUNE register also affect the period of the
WDT by the same factor. For example, if the INTRC
period is increased by 3%, then the WDT period is
increased by 3%.
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and postscaler counts
when executed.
2: Changing the setting of the IRCF bits
(OSCCON<6:4> clears the WDT and
postscaler counts.
3: When a CLRWDT instruction is executed
the postscaler count will be cleared.
4: If WINEN = 0, then CLRWDT must be
executed only when WDTW = 1; other-
wise, a device reset will result.
22.2.1 CONTROL REGISTER
Register 22-15 shows the WDTCON register. This is a
readable and writable register. The SWDTEN bit allows
software to enable or disable the WDT, but only if the
configuration bit has disabled the WDT. The WDTW bit
is a read-only bit that indicates when the WDT count is
in the fourth quadrant (i.e., when the 8-bit WDT value is
b’11000000’ or greater).
FIGURE 22-1:
WDT BLOCK DIAGRAM
SWDTEN
WDTEN
INTRC Source
Enable WDT
INTRC Control
WDT Counter
÷125
Change on IRCF Bits
CLRWDT
All Device Resets
WDTPS<3:0>
Sleep
Programmable Postscaler ^Reset
1:1 to 1:32,768
WDT
4
Wake-up
from Sleep
WDT
Reset
REGISTER 22-15: WDTCON REGISTER
R-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
WDTW
—
—
—
—
—
—
SWDTEN
bit 7
bit 0
bit 7 WDTW: Watchdog Timer Window bit
1 = WDT count is in fourth quadrant
0 = WDT count is not in fourth quadrant
bit 6 Unimplemented
bit 0 SWDTEN: Software Enable / Disable for Watch Dog Timer bit ⁽¹⁾
1 = WDT is turned on
0 = WDT is turned off
Note 1: If WDTEN configuration bit = 1, then WDT is always enabled, irrespective of this control
bit. If WDTEN configuration bit = 0, then it is possible to turn WDT on/off with this con-
trol bit.
Legend:
R = Readable bit
U = Unimplemented bit, read as ‘0’
W = Writable bit
- n = Value at POR
DS39616B-page 278
Preliminary
 2003 Microchip Technology Inc.