PIC18F2331 Datasheet, PDF (69/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2331/2431/4331/4431) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details on
POR, BOR page:
OSCCON
LVDCON
WDTCON
IDLEN
—
WDTW
IRCF2
—
—
IRCF1
IVRST
—
IRCF0
LVDEN
—
OSTS
LVDL3
—
IOFS
LVDL2
—
SCS1
LVDL1
—
SCS0
LVDL0
SWDTEN
0000 q000
--00 0101
0000 0000
28, 49
49, 263
49, 279
RCON
TMR1H
TMR1L
IPEN
—
—
Timer1 register High Byte
Timer1 register Low Byte
RI
TO
PD
POR
BOR
0--1 11qq 47, 74, 105
xxxx xxxx 49, 141
xxxx xxxx 49, 141
T1CON
TMR2
PR2
T2CON
SSPBUF
SSPADD
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
Timer2 register
Timer2 Period register
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
SSP Receive Buffer/Transmit register
SSP Address register in I²C Slave mode. SSP Baud Rate Reload register in I²C Master mode.
0000 0000
0000 0000
1111 1111
-000 0000
xxxx xxxx
0000 0000
49, 137
49, 143
49, 143
49, 143
49, 220
49, 220
SSPSTAT
SSPCON
ADRESH
ADRESL
SMP
CKE
D/A
WCOL
SSPOV
SSPEN
A/D Result register High Byte
A/D Result register Low Byte
P
CKP
S
SSPM3
R/W
SSPM2
UA
SSPM1
BF
SSPM0
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
49, 212
49, 213
50, 259
50, 259
ADCON0
ADCON1
ADCON2
ADCON3
ADCSH
CCPR1H
CCPR1L
CCP1CON
CCPR2H
CCPR2L
CCP2CON
ANSEL1
ANSEL0
T5CON
QEICON
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
RCSTA
BAUDCTL
Legend:
Note 1:
2:
3:
4:
5:
6:
—
—
ACONV ACSCH ACMOD1 ACMOD0 GO/DONE ADON --00 0000 50, 244
VCFG1
VCFG0
—
FIFOEN
BFEMT
FFOVFL ADPNT1 ADPNT0 00-0 1000 ^{50, 245}
ADFM
ACQT3
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0 0000 0000 ^{50, 246}
ADRS1
ADRS0
—
SSRC4
SSRC3
SSRC2
SSRC1
SSRC0 00-0 0000 51. 247
GDSEL1 GDSEL0 GBSEL1 GBSEL0 GCSEL1 GCSEL0 GASEL1 GASEL0 0000 0000 51, 248
Capture/Compare/PWM register1 High Byte
xxxx xxxx 50, 152
Capture/Compare/PWM register1 Low Byte
xxxx xxxx 50, 152
—
—
DC1B1
DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 50, 155,
149
Capture/Compare/PWM register2 High Byte
xxxx xxxx 50, 152
Capture/Compare/PWM register2 Low Byte
xxxx xxxx 50, 152
—
—
DC2B1
DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 50, 155
—
—
—
—
—
—
—
ANS8 ---- ---1 ^{50, 249}
ANS7⁽⁶⁾
ANS6⁽⁶⁾
ANS5⁽⁶⁾
ANS4
ANS3
ANS2
ANS1
ANS0 1111 1111 ^{50, 249}
T5SEN _RESEN⁽⁵⁾ _T5MOD
T5PS1
T5PS0
T5SYNC TMR5CS TMR5ON 0100 0000 ^{50, 145}
VELM
ERROR UP/DOWN QEIM2
QEIM1
QEIM0
PDEC1
PDEC0 0000 0000 ^{50, 171}
Baud Rate Generator register, High Byte
0000 0000 ^{50, 225}
USART Baud Rate Generator
0000 0000 50, 225
USART Receive register
0000 0000 50, 233,
232
USART Transmit register
0000 0000 50, 230,
232
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D 0000 -010 50, 222
SPEN
RX9
SREN
CREN
ADEN
FERR
OERR
RX9D 0000 000x 50, 223
—
RCIDL
—
SCKP
BRG16
—
WUE
ABDEN -1-1 0-00 50, 224
x = unknown, u = unchanged, – = unimplemented, q = value depends on condition
RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator mode only, and read
‘0’ in all other oscillator modes.
RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other modes.
Bit 21 of the PC is only available in Test mode and serial programming modes.
If PBADEN = 0, PORTB<4:0> are configured as digital input and read unknown, and if PBADEN = 1, PORTB<4:0> are configured as
analog input and read ‘0’ following a Reset.
These registers and/or bits are not implemented on the PIC18F2X31 devices, and read as ‘0’.
The RE3 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’. Otherwise, RE3 reads ‘0’. This bit is read-only.
 2003 Microchip Technology Inc.
Preliminary
DS39616B-page 67