PIC18F2331 Datasheet, PDF (163/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
16.1 Input Capture
The Input Capture (IC) submodule implements the
following features:
• Three channels of independent input capture
(16-bits/channel) on the CAP1, CAP2 and CAP3
pins
• Edge-trigger, period or pulse width measurement
operating modes for each channel
• Programmable prescaler on every input capture
channel
• Special event trigger output (IC1 only)
• Selectable noise filters on each capture input
Input channel (IC1) includes a special event trigger
that can be configured for use in Velocity Measure-
ment mode. Its block diagram is shown in Figure 16-2.
IC2 and IC3 are similar, but lack the special event trig-
ger features or additional velocity-measurement logic.
A representative block diagram is shown in
Figure 16-3. Please note that the time base is Timer5.
FIGURE 16-2:
INPUT CAPTURE BLOCK DIAGRAM FOR IC1
CAP1 Pin
Noise
Filter
3
FLTCK<2:0>
1
MUX
0
velcap^{(2) VELM}
Prescaler
1, 4, 16
and
Mode
Select
4
CAP1M<3:0> Q clocks
IC1IF
IC1_TR
Clock/
Reset/
Interrupt
Decode
Logic
CAP1BUF_clk
First Event
Reset
Special
Event
Reset
Q Clocks _CAP1M<3:0>
Clock
CAP1BUF/VELR⁽¹⁾
TMR5
Timer5 Logic
Reset
Reset
Control
Timer
Reset
Control
Timer5 Reset
Note 1: CAP1BUF register is reconfigured as VELR register when QEI mode is active.
2: QEI generated velocity pulses, vel_out, are downsampled to produce this velocity capture signal.
 2003 Microchip Technology Inc.
Preliminary
DS39616B-page 161