PIC18F2331 Datasheet, PDF (258/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
TABLE 20-2: TAD vs. DEVICE OPERATING FREQUENCIES
AD Clock Source (TAD)
Maximum Device Frequency
Operation
ADCS2:ADCS0
PIC18FXX31
PIC18LFXX31⁽⁴⁾
Note 1:
2:
3:
4:
2 TOSC
000
4.8 MHz
666 kHz
4 TOSC
100
9.6 MHz
1.33 MHz
8 TOSC
001
19.2 MHz
2.66 MHz
16 TOSC
101
38.4 MHz
5.33 MHz
32 TOSC
010
40.0 MHz
10.65 MHz
64 TOSC
110
40.0 MHz
21.33 MHz
RC/4⁽³⁾
RC⁽³⁾
011
1.00 MHz⁽¹⁾
1.00 MHz⁽²⁾
111
4.0 MHz⁽²⁾
4.0 MHz⁽²⁾
The RC source has a typical TAD time of 2-6 µs.
The RC source has a typical TAD time of 0.5-1.5 µs.
For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D
accuracy may be out of specification, unless in Single-shot mode.
Low-power devices only.
20.7 Operation in Power-Managed
Modes
The selection of the automatic acquisition time and
A/D conversion clock is determined in part by the
clock source and frequency while in a power-man-
aged mode.
If the A/D is expected to operate while the device is in
a power-managed mode, the ACQT3:ACQT0 and
ADCS2:ADCS0 bits in ADCON2 should be updated in
accordance with the power-managed mode clock that
will be used. After the power-managed mode is entered
(either of the power-managed run modes), an A/D
acquisition or conversion may be started. Once an
acquisition or conversion is started, the device should
continue to be clocked by the same power-managed
mode clock source until the conversion has been com-
pleted. If desired, the device may be placed into the
corresponding power-managed Idle mode during the
conversion.
If the power-managed mode clock frequency is less
than 1 MHz, the A/D RC clock source should be
selected.
Operation in Sleep mode requires the A/D RC clock to
be selected. If bits ACQT3:ACQT0 are set to ‘0000’,
and a conversion is started, the conversion will be
delayed one instruction cycle to allow execution of the
SLEEP instruction and entry to Sleep mode. The IDLEN
and SCS bits in the OSCCON register must have
already been cleared prior to starting the conversion.
Note:
The A/D can operate in Sleep mode only
when configured for Single-shot opera-
tion. If the part is in Sleep mode, and it is
possible for a source other than the A/D
module to wake the part, the user must
poll ADCON<GO/DONE> to ensure it is
clear before reading the result.
20.8 Configuring Analog Port Pins
The ANSEL0, ANSEL1, TRISA and TRISE registers all
configure the A/D port pins. The port pins needed as
analog inputs must have their corresponding TRIS bits
set (input). If the TRIS bit is cleared (output), the digital
output level (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
ANSEL0, ANSEL1 and the TRIS bits.
Note 1: When reading the Port register, all pins
configured as analog input channels will
read as cleared (a low level). Pins
configured as digital inputs will convert an
analog input. Analog levels on a digitally
configured input will be accurately
converted.
2: Analog levels on any pin defined as a
digital input may cause the digital input
buffer to consume current out of the
device’s specification limits.
DS39616B-page 256
Preliminary
 2003 Microchip Technology Inc.