PIC18F2331 Datasheet, PDF (51/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
FSR1H
2331 2431 4331 4431 ---- xxxx
---- uuuu
---- uuuu
FSR1L
2331 2431 4331 4431 xxxx xxxx
uuuu uuuu
uuuu uuuu
BSR
2331 2431 4331 4431 ---- 0000
---- 0000
---- uuuu
INDF2
2331 2431 4331 4431
N/A
N/A
N/A
POSTINC2 2331 2431 4331 4431
N/A
N/A
N/A
POSTDEC2 2331 2431 4331 4431
N/A
N/A
N/A
PREINC2 2331 2431 4331 4431
N/A
N/A
N/A
PLUSW2 2331 2431 4331 4431
N/A
N/A
N/A
FSR2H
2331 2431 4331 4431 ---- xxxx
---- uuuu
---- uuuu
FSR2L
2331 2431 4331 4431 xxxx xxxx
uuuu uuuu
uuuu uuuu
STATUS
2331 2431 4331 4431 ---x xxxx
---u uuuu
---u uuuu
TMR0H
2331 2431 4331 4431 0000 0000
0000 0000
uuuu uuuu
TMR0L
2331 2431 4331 4431 xxxx xxxx
uuuu uuuu
uuuu uuuu
T0CON
2331 2431 4331 4431 11-- 1111
11-- 1111
uu-- uuuu
OSCCON 2331 2431 4331 4431 0000 0000
0000 0000
uuuu uuuu
LVDCON 2331 2431 4331 4431 --00 0101
--00 0101
--uu uuuu
WDTCON
RCON⁽⁴⁾
2331 2431 4331 4431
2331 2431 4331 4431
---- ---0
0--1 11q0
---- ---0
0--q qquu
---- ---u
u--u qquu
TMR1H
2331 2431 4331 4431 xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1L
2331 2431 4331 4431 xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
2331 2431 4331 4431 0000 0000
u0uu uuuu
uuuu uuuu
TMR2
2331 2431 4331 4431 0000 0000
0000 0000
uuuu uuuu
PR2
2331 2431 4331 4431 1111 1111
1111 1111
1111 1111
T2CON
2331 2431 4331 4431 -000 0000
-000 0000
-uuu uuuu
SSPBUF
2331 2431 4331 4431 xxxx xxxx
uuuu uuuu
uuuu uuuu
SSPADD 2331 2431 4331 4431 0000 0000
0000 0000
uuuu uuuu
SSPSTAT 2331 2431 4331 4431 0000 0000
0000 0000
uuuu uuuu
SSPCON 2331 2431 4331 4431 0000 0000
0000 0000
uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-2 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the Oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6: Bit 3 of PORTE and LATE are enabled if MCLR functionality is disabled. When not enabled as the PORTE
pin, they are disabled and read as ‘0’. The 28-pin devices have only RE3 on PORTE when MCLR is
disabled.
 2003 Microchip Technology Inc.
Preliminary
DS39616B-page 49