PIC18F2331 Datasheet, PDF(222/396 Page) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

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PIC18F2331 Datasheet, PDF (222/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

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PIC18F2331/2431/4331/4431

18.3.2 MASTER MODE

Master mode of operation is supported in firmware

using interrupt generation on the detection of the Start

and Stop conditions. The Stop (P) and Start (S) bits are

cleared from a Reset or when the SSP module is

disabled. The Stop (P) and Start (S) bits will toggle

based on the Start and Stop conditions. Control of the

I2C bus may be taken when the P bit is set, or the bus

is Idle and both the S and P bits are clear.

In Master mode, the SCL and SDA lines are manipu-

lated by clearing the corresponding TRISC<5:4> or

TRISD<3:2> bits. The output level is always low, irre-

spective of the value(s) in PORTC<5:4> or

PORTD<3:2>. So when transmitting data, a '1' data bit

must have the TRISC<4> bit set (input) and a '0' data

bit must have the TRISC<4> bit cleared (output). The

same scenario is true for the SCL line with the

TRISC<4> or TRISD<2> bit. Pull-up resistors must be

provided externally to the SCL and SDA pins for proper

operation of the I2C module.

The following events will cause SSP interrupt flag bit,

SSPIF, to be set (SSP Interrupt will occur if enabled):

â¢ Start condition

â¢ Stop condition

â¢ Data transfer byte transmitted/received

Master mode of operation can be done with either the

Slave mode Idle (SSPM3:SSPM0 = 1011), or with the

Slave active. When both Master and Slave modes are

enabled, the software needs to differentiate the

source(s) of the interrupt.

18.3.3 MULTI-MASTER MODE

In Multi-Master mode, the interrupt generation on the

detection of the Start and Stop conditions, allows the

determination of when the bus is free. The Stop (P) and

Start (S) bits are cleared from a Reset or when the SSP

module is disabled. The Stop (P) and Start (S) bits will

toggle based on the Start and Stop conditions. Control

of the I2C bus may be taken when bit P (SSPSTAT<4>)

is set, or the bus is Idle and both the S and P bits clear.

When the bus is busy, enabling the SSP interrupt will

generate the interrupt when the Stop condition occurs.

In Multi-Master operation, the SDA line must be moni-

tored to see if the signal level is the expected output

level. This check only needs to be done when a high

level is output. If a high level is expected and a low level

is present, the device needs to release the SDA and

SCL lines (set TRISC<5:4> or TRISD<3:2> ). There are

two stages where this arbitration can be lost, these are:

â¢ Address Transfer

â¢ Data Transfer

When the slave logic is enabled, the slave continues to

receive. If arbitration was lost during the address trans-

fer stage, communication to the device may be in

progress. If addressed, an ACK pulse will be gener-

ated. If arbitration was lost during the data transfer

stage, the device will need to retransfer the data at a

later time.

TABLE 18-3: REGISTERS ASSOCIATED WITH I2C OPERATION

Name

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on

all other

Resets

INTCON

PIR1

PIE1

GIE

PSPIF(1)

PSPIE(1)

PEIE TMR0IE INTE

ADIF RCIF TXIF

ADIE RCIE TXIE

RBIE TMR0IF INTF RBIF

SSPIF CCP1IF TMR2IF TMR1IF

SSPIE CCP1IE TMR2IE TMR1IE

0000 000x

0000 0000

0000 0000

0000 000u

0000 0000

0000 0000

SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register

SSPADD Synchronous Serial Port (I2C mode) Address Register

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

SSPCON WCOL SSPOV SSPEN CKP

SSPSTAT SMP(2) CKE(2) D/A

P

TRISC(3) PORTC Data Direction Register

TRISD(3) PORTD Data Direction Register

SSPM3 SSPM2 SSPM1 SSPM0

S

R/W UA

BF

0000 0000

0000 0000

1111 1111

1111 1111

0000 0000

0000 0000

1111 1111

1111 1111

Legend:

Note 1:

2:

3:

x = unknown, u = unchanged, â = unimplemented locations read as â0â. Shaded cells are not used by SSP

module in I2C mode.

PSPIF and PSPIE are reserved on the PIC16F73/76; always maintain these bits clear.

Maintain these bits clear in I2C mode.

Depending upon the setting of SSPMX in CONFIG3H, these pins are multiplexed to PORTC or PORTD.

DS39616B-page 220

Preliminary

ï£© 2003 Microchip Technology Inc.

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