PIC18F2331 Datasheet, PDF (285/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
22.5 Program Verification and
Code Protection
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PICmicro^® devices.
The user program memory is divided into five blocks.
One of these is a boot block of 512 bytes. The
remainder of the memory is divided into four blocks on
binary boundaries.
Each of the five blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 22-5 shows the program memory organization
for 8- and 16-Kbyte devices, and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 22-3.
FIGURE 22-5:
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2331/2431/4331/4431
MEMORY SIZE/DEVICE
Block Code Protection
Controlled By:
8 Kbytes
(PIC18FX331)
Boot Block
Block 0
Block 1
Address
Range
0000h
0FFFh
0200h
0FFFh
1000h
1FFFh
Unimplemented
Read 0’s
3FFFh
16 Kbytes
(PIC18FX431)
Boot Block
Block 0
Block 1
Block 2
Block 3
Address
Range
0000h
01FFh
0200h
0FFFh
1000h
1FFFh
2000h
2FFFh
3000h
3FFFh
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1
CP2, WRT2, EBTR2
CP3, WRT3, EBTR3
TABLE 22-3: SUMMARY OF CODE PROTECTION REGISTERS
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
300008h
300009h
30000Ah
30000Bh
30000Ch
30000Dh
Legend:
CONFIG5L —
—
CONFIG5H CPD
CPB
CONFIG6L —
—
CONFIG6H WRTD WRTB
CONFIG7L —
—
CONFIG7H —
EBTRB
Shaded cells are unimplemented.
—
—
—
WRTC
—
—
—
CP3
—
—
—
WRT3
—
—
—
EBTR3
—
—
Bit 2
CP2
—
WRT2
—
EBTR2
—
Bit 1
CP1
—
WRT1
—
EBTR1
—
Bit 0
CP0
—
WRT0
—
EBTR0
—
 2003 Microchip Technology Inc.
Preliminary
DS39616B-page 283