PIC18F2331 Datasheet, PDF (390/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
LVDCON (LVD Control) ........................................... 263
OSCCON (Oscillator Control) .................................... 28
OSCTUNE (Oscillator Tuning) ................................... 25
PIE1 (Peripheral Interrupt Enable 1) .......................... 99
PIE2 (Peripheral Interrupt Enable 2) ........................ 100
PIR1 (Peripheral Interrupt Request (Flag) 1) ............. 96
PIR2 (Peripheral Interrupt Request (Flag) 2) ............. 97
RCON (Reset Control) ....................................... 74, 105
RCSTA (Receive Status and Control) ...................... 223
SSPCON (Sync Serial Port Control) Register .......... 213
SSPSTAT (Sync Serial Port Status) Register .......... 212
Status ......................................................................... 73
STKPTR (Stack Pointer) ............................................ 59
Summary .............................................................. 66–68
T0CON (Timer0 Control) .......................................... 133
T1CON (Timer 1 Control) ......................................... 137
T2CON (Timer 2 Control) ......................................... 143
TRISE ....................................................................... 131
TXSTA (Transmit Status and Control) ..................... 222
WDTCON (Watchdog Timer Control) ....................... 278
Reset .......................................................................... 45, 317
Resets .............................................................................. 267
RETFIE ............................................................................ 318
RETLW ............................................................................. 318
RETURN .......................................................................... 319
Return Address Stack ........................................................ 58
Return Stack Pointer (STKPTR) ........................................ 58
Revision History ............................................................... 379
RLCF ................................................................................ 319
RLNCF ............................................................................. 320
RRCF ............................................................................... 320
RRNCF ............................................................................. 321
S
S (Start) bit ....................................................................... 212
SCK .................................................................................. 211
SCL .................................................................................. 217
SDI ................................................................................... 211
SDO ................................................................................. 211
Serial Clock (SCK) Pin ..................................................... 211
Serial Data In (SDI) Pin .................................................... 211
Serial Data Out (SDO) Pin ............................................... 211
SETF ................................................................................ 321
Slave Select (SS) Pin ....................................................... 211
Sleep ................................................................................ 322
OSC1 and OSC2 Pin States ...................................... 29
SMP bit ............................................................................. 212
Software Simulator (MPLAB SIM) .................................... 332
Software Simulator (MPLAB SIM30) ................................ 332
Special Event Trigger. See Compare (CCP Module).
Special Features of the CPU ............................................ 267
Special Function Registers ................................................ 65
Map ............................................................................ 65
SPI Mode ......................................................................... 211
Associated Registers ............................................... 216
Serial Clock .............................................................. 211
Serial Data In ........................................................... 211
Serial Data Out ......................................................... 211
Slave Select ............................................................. 211
SS .................................................................................... 211
SSP
Overview
TMR2 Output for Clock Shift ............................ 143, 144
SSP I²C Operation ........................................................... 217
Slave Mode .............................................................. 217
SSPEN Bit ........................................................................ 213
DS39616B-page 388
SSPM<3:0> Bits .............................................................. 213
SSPOV Bit ....................................................................... 213
Stack Full/Underflow Resets .............................................. 59
SUBFWB ......................................................................... 322
SUBLW ............................................................................ 323
SUBWF ............................................................................ 323
SUBWFB ......................................................................... 324
SWAPF ............................................................................ 325
Synchronous Serial Port Enable Bit (SSPEN) ................. 213
Synchronous Serial Port Mode Select Bits
(SSPM<3:0>) ........................................................... 213
Synchronous Serial Port. See SSP.
T
TABLAT Register ............................................................... 78
Table Pointer Operations (table) ........................................ 78
Table Reads/Table Writes ................................................. 63
TBLPTR Register ............................................................... 78
TBLRD ............................................................................. 326
TBLWT ............................................................................. 327
Time-out in Various Situations (table) ................................ 47
Timer0 .............................................................................. 133
16-bit Mode Timer Reads and Writes ...................... 135
Associated Registers ............................................... 135
Clock Source Edge Select (T0SE Bit) ..................... 135
Clock Source Select (T0CS Bit) ............................... 135
Interrupt ................................................................... 135
Operation ................................................................. 135
Prescaler. See Prescaler, Timer0.
Switching Prescaler Assignment ............................. 135
Timer1 .............................................................................. 137
16-bit Read/Write Mode ........................................... 140
Associated Registers ............................................... 141
Interrupt ................................................................... 140
Operation ................................................................. 138
Oscillator ...........................................................137, 139
Oscillator Layout Considerations ............................. 139
Overflow Interrupt .................................................... 137
Resetting, Using a Special Event Trigger
Output (CCP) ................................................... 140
Special Event Trigger (CCP) ................................... 154
TMR1H Register ...................................................... 137
TMR1L Register ....................................................... 137
Use as a Real-Time Clock ....................................... 140
Timer2 .............................................................................. 143
Associated Registers ............................................... 144
Operation ................................................................. 143
Postscaler. See Postscaler, Timer2.
PR2 Register ....................................................143, 156
Prescaler. See Prescaler, Timer2.
SSP Clock Shift ................................................143, 144
TMR2 Register ......................................................... 143
TMR2 to PR2 Match Interrupt ...................143, 144, 156
Timer5
Block Diagram ......................................................... 146
Timing Diagrams
Asynchronous Reception ......................................... 234
Asynchronous Transmission .................................... 231
Asynchronous Transmission (Back to Back) ........... 231
Auto-Wake-up Bit (WUE) During
Normal Operation ............................................ 235
Auto-Wake-up Bit (WUE) During Sleep ................... 235
Brown-out Reset (BOR) ........................................... 358
Capture/Compare/PWM (CCP) ............................... 360
CLKO and I/O .......................................................... 357
Clock, Instruction Cycle ............................................. 61
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