PIC18F2331 Datasheet, PDF (366/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
FIGURE 25-14:
SS
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
70
SCK
83
(CKP = 0)
71
72
SCK
(CKP = 1)
80
SDO
MSb
bit6 - - - - - -1
LSb
75, 76
77
SDI
MSb IN
bit6 - - - -1
LSb IN
74
Note: Refer to Figure 25-4 for load conditions.
TABLE 25-14: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TssL2scH, SS↓ to SCK↓ or SCK↑ input
TssL2scL
TCY
—
71
TscH
71A
SCK input high time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
72
TscL
72A
SCK input low time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
73A TB2B
Last clock edge of Byte1 to the first clock edge of Byte2 1.5 TCY + 40 —
74
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
100
—
75
TdoR
SDO data output rise time
PIC18FXX31
—
25
PIC18LFXX31
45
76
TdoF
SDO data output fall time
—
25
77
TssH2doZ SS↑ to SDO output hi-impedance
10
50
78
TscR
SCK output rise time
(Master mode)
PIC18FXX31
PIC18LFXX31
—
25
—
45
79
TscF
SCK output fall time (Master mode)
—
25
80
TscH2doV, SDO data output valid after SCK PIC18FXX31
TscL2doV edge
PIC18LFXX31
—
50
—
100
82
TssL2doV SDO data output valid after SS↓ PIC18FXX31
edge
PIC18LFXX31
—
50
—
100
83
TscH2ssH, SS ↑ after SCK edge
TscL2ssH
1.5 TCY + 40 ^—
Note 1: Requires the use of Parameter # 73A.
2: Only if Parameter # 71A and # 72A are used.
ns
ns
ns (Note 1)
ns
ns (Note 1)
ns (Note 2)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS39616B-page 364
Preliminary
 2003 Microchip Technology Inc.