PIC18F2331 Datasheet, PDF (90/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
7.7 Operation During Code-Protect
Data EEPROM memory has its own code-protect bits in
configuration words. External Read and Write opera-
tions are disabled if either of these mechanisms are
enabled.
The microcontroller itself can both read and write to the
internal data EEPROM, regardless of the state of the
code-protect configuration bit. Refer to Section 22.0
“Special Features of the CPU” for additional
information.
7.8 Using the Data EEPROM
The Data EEPROM is a high-endurance, byte
addressable array that has been optimized for the
storage of frequently changing information (e.g.,
program variables or other data that are updated
often). Frequently changing values will typically be
updated more often than specification D124 or D124A.
If this is not the case, an array refresh must be
performed. For this reason, variables that change
infrequently (such as constants, IDs, calibration, etc.)
should be stored in Flash program memory.
A simple data EEPROM refresh routine is shown in
Example 7-3.
Note:
If data EEPROM is only used to store con-
stants and/or data that changes rarely, an
array refresh is likely not required. See
specification D124 or D124A.
EXAMPLE 7-3: DATA EEPROM REFRESH ROUTINE
LOOP
CLRF
BCF
BCF
BCF
BSF
EEADR
EECON1, CFGS
EECON1, EEPGD
INTCON, GIE
EECON1, WREN
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BTFSC
BRA
INCFSZ
BRA
EECON1, RD
55h
EECON2
AAh
EECON2
EECON1, WR
EECON1, WR
$-2
EEADR, F
Loop
; Start at address 0
; Set for memory
; Set for Data EEPROM
; Disable interrupts
; Enable writes
; Loop to refresh array
; Read current address
;
; Write 55h
;
; Write AAh
; Set WR bit to begin write
; Wait for write to complete
; Increment address
; Not zero, do it again
BCF
EECON1, WREN
BSF
INTCON, GIE
; Disable writes
; Enable interrupts
TABLE 7-1: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
Resets
INTCON
EEADR
EEDATA
EECON2
EECON1
IPR2
PIR2
PIE2
Legend:
GIE/GIEH PEIE/GIEL TMR0IE INTE RBIE TMR0IF INTF
EEPROM Address Register
EEPROM Data Register
EEPROM Control Register2 (not a physical register)
EEPGD
CFGS
—
FREE WRERR WREN WR
OSFIP
—
—
EEIP
—
LVDIP
—
OSFIF
—
—
EEIF
—
LVDIF
—
OSFIE
—
—
EEIE
—
LVDIE
—
x = unknown, u = unchanged, r = reserved, - = unimplemented, read as ‘0’.
Shaded cells are not used during Flash/EEPROM access.
RBIF 0000 000x 0000 000u
0000 0000 0000 0000
0000 0000 0000 0000
—
—
RD xx-0 x000 uu-0 u000
CCP2IP 1--1 -1-1 1--1 -1-1
CCP2IF 0--0 -0-0 0--0 -0-0
CCP2IE 0--0 -0-0 0--0 -0-0
DS39616B-page 88
Preliminary
 2003 Microchip Technology Inc.