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PIC18F2331 Datasheet, PDF (50/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D
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PIC18F2331/2431/4331/4431
TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
TOSU
TOSH
TOSL
STKPTR
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
uu-0 0000
---0 uuuu(3)
uuuu uuuu(3)
uuuu uuuu(3)
uu-u uuuu(3)
PCLATU
2331 2431 4331 4431 ---0 0000
---0 0000
---u uuuu
PCLATH
PCL
2331 2431 4331 4431
2331 2431 4331 4431
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PC + 2(2)
TBLPTRU 2331 2431 4331 4431 --00 0000
--00 0000
--uu uuuu
TBLPTRH 2331 2431 4331 4431 0000 0000
0000 0000
uuuu uuuu
TBLPTRL 2331 2431 4331 4431 0000 0000
0000 0000
uuuu uuuu
TABLAT
2331 2431 4331 4431 0000 0000
0000 0000
uuuu uuuu
PRODH
2331 2431 4331 4431 xxxx xxxx
uuuu uuuu
uuuu uuuu
PRODL
INTCON
INTCON2
INTCON3
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
xxxx xxxx
0000 000x
1111 -1-1
11-0 0-00
uuuu uuuu
0000 000u
1111 -1-1
11-0 0-00
uuuu uuuu
uuuu uuuu(1)
uuuu -u-u(1)
uu-u u-uu(1)
INDF0
2331 2431 4331 4431
N/A
N/A
N/A
POSTINC0 2331 2431 4331 4431
N/A
N/A
N/A
POSTDEC0 2331 2431 4331 4431
N/A
N/A
N/A
PREINC0 2331 2431 4331 4431
N/A
N/A
N/A
PLUSW0 2331 2431 4331 4431
N/A
N/A
N/A
FSR0H
2331 2431 4331 4431 ---- xxxx
---- uuuu
---- uuuu
FSR0L
2331 2431 4331 4431 xxxx xxxx
uuuu uuuu
uuuu uuuu
WREG
2331 2431 4331 4431 xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF1
2331 2431 4331 4431
N/A
N/A
N/A
POSTINC1 2331 2431 4331 4431
N/A
N/A
N/A
POSTDEC1 2331 2431 4331 4431
N/A
N/A
N/A
PREINC1 2331 2431 4331 4431
N/A
N/A
N/A
PLUSW1 2331 2431 4331 4431
N/A
N/A
N/A
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-2 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the Oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6: Bit 3 of PORTE and LATE are enabled if MCLR functionality is disabled. When not enabled as the PORTE
pin, they are disabled and read as ‘0’. The 28-pin devices have only RE3 on PORTE when MCLR is
disabled.
DS39616B-page 48
Preliminary
 2003 Microchip Technology Inc.
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