PIC18F2331 Datasheet, PDF (185/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
FIGURE 17-2:
PWM MODULE BLOCK DIAGRAM, ONE OUTPUT PAIR, COMPLEMENTARY
MODE
Duty Cycle Comparator
PWM Duty Cycle Register
Fault A pin
Fault B pin
Fault Override Values
Channel Override Values
Fault Pin Assignment
Logic
VDD
Dead-Band
Generator
HPOL
LPOL
PWM1
PWM0
Note:
In the Complementary mode, the even channel cannot be
forced active by a fault or override event when the odd channel
is active. The even channel is always the complement of the
odd channel and is inactive, with dead time inserted, before
the odd channel is driven to its active state.
FIGURE 17-3:
PWM MODULE BLOCK DIAGRAM, ONE OUTPUT PAIR, INDEPENDENT MODE
VDD
PWM Duty Cycle Register
Duty Cycle Comparator
PWM1
VDD
HPOL
Fault A pin
Fault B pin
Fault Override Values
Channel Override Values
Fault Pin Assignment
Logic
This module contains four duty-cycle generators,
numbered 0 through 3. The module has eight PWM
output pins, numbered 0 through 7. The eight PWM
outputs are grouped into output pairs of even and odd
numbered outputs. In complimentary modes, the even
PWM pins must always be the complement of the
corresponding odd PWM pin. For example, PWM0 will
be the complement of PWM1, PWM2 will be the
complement of PWM3, and so on. The dead time
LPOL
PWM0
generator inserts an “off” period called “dead time”
between the going off of one pin to the going on of the
complementary pin of the paired pins. This is to prevent
damage to the power switching devices that will be
connected to the PWM output pins.
The time base for the PWM module is provided by its
own 12-bit timer, which also incorporates selectable
prescaler and postscaler options.
 2003 Microchip Technology Inc.
Preliminary
DS39616B-page 183