PIC18F2331 Datasheet, PDF (68/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2331/2431/4331/4431)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details on
POR, BOR page:
TOSU
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000 48, 58
TOSH
Top-of-Stack High Byte (TOS<15:8>)
0000 0000 48, 58
TOSL
Top-of-Stack Low Byte (TOS<7:0>)
0000 0000 48, 58
STKPTR
PCLATU
STKFUL
—
STKUNF
—
—
Return Stack Pointer
bit 21⁽³⁾ Holding register for PC<20:16>
00-0 0000
---0 0000
48, 59
48, 60
PCLATH
Holding register for PC<15:8>
0000 0000 48, 60
PCL
TBLPTRU
PC Low Byte (PC<7:0>)
—
—
bit 21⁽³⁾ Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
0000 0000
--00 0000
48, 60
48, 78
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
0000 0000 48, 78
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
0000 0000 48, 78
TABLAT
Program Memory Table Latch
0000 0000 48, 78
PRODH
Product register High Byte
xxxx xxxx 48, 89
PRODL
Product register Low Byte
xxxx xxxx 48, 89
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
INT0F
RBIF 0000 000x 48, 93
INTCON2
RBPU INTEDG0 INTEDG1 INTEDG2
—
TMR0IP
—
RBIP 1111 -1-1 48, 94
INTCON3
INT2P
INT1P
—
INT2IE
INT1IE
—
INT2IF
INT1IF 11-0 0-00 48, 95
INDF0
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
N/A
48, 71
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
N/A
48, 71
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
N/A
48, 71
PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
N/A
48, 71
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 offset by W (not a physical register)
N/A
48, 71
FSR0H
—
—
—
—
Indirect Data Memory Address Pointer 0 High
---- 0000 48, 71
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
xxxx xxxx 48, 71
WREG
Working register
xxxx xxxx
48
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
N/A
48, 71
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
N/A
48, 71
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
N/A
48, 71
PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
N/A
48, 71
PLUSW1
Uses contents of FSR1 to address data memory – value of FSR1 offset by W (not a physical register)
N/A
48, 71
FSR1H
—
—
—
—
Indirect Data Memory Address Pointer 1 High
---- 0000 49, 71
FSR1L
Indirect Data Memory Address Pointer 1 Low Byte
xxxx xxxx 49, 71
BSR
—
—
—
—
Bank Select Register
---- 0000 49, 70
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
N/A
49, 71
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
N/A
49, 71
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
N/A
49, 71
PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
N/A
49, 71
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 offset by W (not a physical register)
N/A
49, 71
FSR2H
—
—
—
—
Indirect Data Memory Address Pointer 2 High
---- 0000 49, 71
FSR2L
Indirect Data Memory Address Pointer 2 Low Byte
xxxx xxxx 49, 71
STATUS
—
—
—
N
OV
Z
DC
C
---x xxxx 49, 73
TMR0H
Timer0 register High Byte
0000 0000 49, 135
TMR0L
Timer0 register Low Byte
xxxx xxxx 49, 135
T0CON
TMR0ON T016BIT
—
—
T0PS3
T0PS2
T0PS1
T0PS0 11-- 1111 49, 133
Legend:
Note 1:
2:
3:
4:
5:
6:
x = unknown, u = unchanged, – = unimplemented, q = value depends on condition
RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator mode only, and read
‘0’ in all other oscillator modes.
RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other modes.
Bit 21 of the PC is only available in Test mode and serial programming modes.
If PBADEN = 0, PORTB<4:0> are configured as digital input and read unknown, and if PBADEN = 1, PORTB<4:0> are configured as
analog input and read ‘0’ following a Reset.
These registers and/or bits are not implemented on the PIC18F2X31 devices, and read as ‘0’.
The RE3 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’. Otherwise, RE3 reads ‘0’. This bit is read-only.
DS39616B-page 66
Preliminary
 2003 Microchip Technology Inc.