PIC18F2331 Datasheet, PDF (165/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
The three Input Capture channels are controlled
through the Input Capture Control Registers
CAP1CON, CAP2CON, and CAP3CON. Each channel
is configured independently with its dedicated register.
The implementation of the registers is identical, except
for the Special Event trigger (see Section 16.1.8 “Spe-
cial Event Trigger (CAP1 Only)”). The typical Capture
Control register is shown in Register 16-1.
REGISTER 16-1:
CAPxCON: INPUT CAPTURE CONTROL REGISTER
U-0
R/W-0
U-0
R/W-0 R/W-0 R/W-0
— CAPxREN —
—
CAPxM3 CAPxM2
bit 7
R/W-0
CAPxM1
R/W-0
CAPxM0
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3-0
Unimplemented: Read as ‘0’
CAPxREN: Time Base Reset Enable bit
1 = Enabled
0 = Disable selected time base Reset on capture.
Unimplemented: Read as ‘0’
Unimplemented: Read as ‘0’
CAPxM3:CAPxM0: Input Capture 1 (ICx) Mode Select bits
1111 = Special Event Trigger mode. The trigger occurs on every rising edge on CAP1 input⁽¹⁾
1110 = Special Event Trigger mode. The trigger occurs on every falling edge on CAP1 input⁽¹⁾
1101 = Unused
1100 = Unused
1011 = Unused
1010 = Unused
1001 = Unused
1000 = Capture on every CAPx input state change
0111 = Pulse Width Measurement mode, every rising to falling edge
0110 = Pulse Width Measurement mode, every falling to rising edge
0101 = Frequency Measurement mode, every rising edge
0100 = Capture mode, every 16th rising edge
0011 = Capture mode, every 4th rising edge
0010 = Capture mode, every rising edge
0001 = Capture mode, every falling edge
0000 = Input Capture 1 (ICx) off
Note 1: Special Event Trigger is only available on CAP1. For CAP2 and CAP3, this config-
uration is unused.
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
Note:
Throughout this section, references to
registers and bit names that may be asso-
ciated with a specific capture channel will
be referred to generically by the use of the
term ‘x’ in place of the channel number.
For example, ‘CAPxREN’ may refer to the
Capture Reset Enable bit in CAP1CON,
CAP2CON or CAP3CON.
When in Counter mode, the counter must be
configured as the synchronous counter only
(TMR5SYNC = 0). When configured in Asynchronous
mode, the IC module will not work properly.
 2003 Microchip Technology Inc.
Preliminary
DS39616B-page 163